Dual port semiconductor memory device

Details Dual port semiconductor memory device Dual port semiconductor memory device

2006-10-10

2006-10-10

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S063000, C365S154000, C257S371000, C711S131000, C711S149000

Reexamination Certificate

active

07120080

ABSTRACT:
A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

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English language abstract of Japanese Publication No. 10-178110.
English language abstract of Korean Publication No. 2001-0106233.

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