Dual port random-access-memory circuitry

Details Dual port random-access-memory circuitry Dual port random-access-memory circuitry

2006-08-18

2008-12-30

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S226000

Reexamination Certificate

active

07471588

ABSTRACT:
Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.

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“Circuit Techniques for High-Speed and Low-Power Multi-Port SRAMS”. Muhammad M. Khellah and M. I. Elmasry. ASIC Conference 1998. Sep. 13, 1998.

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