Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
1998-08-28
2001-07-03
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C365S189040, C365S149000
Reexamination Certificate
active
06256256
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to electronic memories and in particular to dual port random access memories and systems using the same.
BACKGROUND OF THE INVENTION
There are numerous ways in which a dynamic random access memories (DRAMs) are traditionally constructed, using variations in process, circuit designs, and system architecture. By varying these parameters, various problems related to device size and performance can be addressed. None the less, all currently available DRAMs are generally based upon architectures which share the following disadvantageous characteristics.
First, the typical general purpose DRAM has a single data port for writing and reading data to and from addressed storage locations (“dual ported” DRAMs are available which provide two data ports, typically one random and one serial port, however, these devices are normally limited to special memory applications). Second, data writes and reads are only made to a given array on a location by location (e.g. one bit, one byte, one word) basis and only during the array active cycle. Specifically, in a “random access mode”, an access (read or write) is made to a single location per row address strobe (/RAS) active cycle and in a “page mode” an access is made to a single location per column address strobe (/CAS) or master clock cycle of the row addressed during the given /RAS cycle. During the inactive cycle, the array is in precharge and no accesses can be made to that array.
Third, no method has generally been established to handle contention problems which arise when simultaneous requests for access are made to the same DRAM unit. Current techniques for handling contention problems depend on the DRAM and/or system architecture selected by the designer and range, for example, from “uniform memory-noncontention” methods to “non-uniform memory access” (NUMA) methods.
Similarly, the system architectures of personal computers (PC's) generally share a number of common features. For example, the vast majority of today's PC's are built around a single central processing unit (CPU), which is the system “master.” All other subsystems, such as the display controller, disk drive controller, and audio controller then operate as slaves to the CPU. This master/slave organization is normally used no matter whether the CPU is a complex instruction set computer (CISC), reduced instruction set computer (RISC), Silicon Graphics MIPS device or Digital Equipment ALPHA device.
Present memory and PC architectures, such as those discussed above, are rapidly becoming inadequate for constructing the fast machines with substantial storage capacity required to run increasingly sophisticated application software. The problem has already been addressed, at least in part, in the mainframe and server environments by the use of multiprocessor (multiprocessing) architectures. Multiprocessing architectures however are not yet cost effective for application in the PC environment. Furthermore, memory contention and bus contention are still significant concerns in any multiprocessing system, let alone in a multiprocessing PC environment.
Thus, the need has arisen for new memories for use in high speed and/or multiprocessing systems. Preferably, such memories should have a “transparent” precharge and/or multiple random access ports. Additionally, these memories should be capable of use in addressing memory contention problems, especially those occurring in multiprocessing systems.
SUMMARY OF THE INVENTION
According to one embodiment of the principles of the present invention, a memory is disclosed including an array of rows and columns of memory cells, each row associated with first and second wordlines and each column associated with first and second bitlines. A first port is used for accessing selected ones of the memory cells using the first word line and the first bitlines of corresponding rows and columns, the first port associated with first dedicated sets of address, data, clock and control signal terminals for supporting accesses by a first processing device using a time base and an access-type required by the first processing device. A second port is used for accessing selected ones of the memory cells using the second wordline and the second bitline of corresponding ones of the rows and columns, the second port associated with second dedicated sets of address, data, clock and control signal terminals for supporting access by a second processing device using a time base and an access type required by the second processing device.
Further principles of the present inventions are embodied in a frame buffer having a first port with dedicated address, data and control signal inputs for updating display data within the memory using timing parameters and access types optimized for use with a selected processing device and a second port having dedicated address, data and control signal inputs for supporting simultaneous and asynchronous accesses to the frame buffer by a display controller.
Also a system is also disclosed which includes a first processing device operating in accordance with first clock and a first set of memory access parameters and a second processing device operating in accordance with a second clock and a second set of memory access parameters. The system also includes a multiport memory including first and second ports. First port is coupled to the first processing device and operating in accordance with the first clock and the first set of access parameters. The second port is coupled to the second processing device and operating in accordance with the second clock and the second set of access parameters. Memory includes an array of rows and columns of memory cells, each memory cell including a capacitor and first and second pass transistors, the first pass transistor for coupling the capacitor to a first bitline in response to an active signal on a first wordline and the second pass transistor coupling the capacitor to a second bitline in response to an active signal on a second wordline, the first port accessing a selected cell using the first bitline and the first wordline and the second port accessing a selected cell using the second bitline and the second wordline.
The present inventive concepts provide substantial advantages over the prior art. Among other things, two different processing resources can simultaneously access the same memory. Additionally, different processing resources can use different types of memory accesses through the different ports simultaneously. Finally, those processing resources can perform simultaneous accesses using different timing parameters.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
REFERENCES:
patent: 4203159 (1980-05-01), Wanlass
patent: 5007022 (1991-04-01), Leigh
patent: 5010519 (1991-04-01), Yoshimoto et al.
patent: 5500654 (1996-03-01), Fujimoto
“Transparent-Refresh DRAM (TreD) Using Dual-Port DRAM Cell” by Sakurai, Nogami, Sawada and Iizuka, 1988 IEEE Custom Integrated Circuits Conference p. 4.3.1 through4.3.4.
Hoang Huan
Murphy, Esq. James J.
Silicon Aquarius, Inc.
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