Dual port multiple block memory capable of time divisional opera

Details Dual port multiple block memory capable of time divisional opera Dual port multiple block memory capable of time divisional opera

1994-12-23

1996-08-06

Lane, Jack A.

Static information storage and retrieval

Read/write circuit

365154, 36518905, 36523003, 36523005, G11C 700

Patent

active

055440932

ABSTRACT:
A plurality of bit line pairs are divided into plural bit line groups. Each of the bit line groups comprises two bit line pairs. The two bit line pairs are respectively connected to a common sense amplifier through transistors. The two bit line pairs are respectively connected to a common data register via transistors. Either one of the two bit line pairs is connected to the sense amplifier by a switching signal. In addition, either one of the two bit line pairs is connected to the data register by a data transfer signal. One of the two bit line pairs in one of bit line groups and one of the two bit line pairs in the remaining bit line groups constitute a block. The other of the two bit line pairs in one of bit line groups and the other of the two bit line pairs in the remaining bit line groups constitute another block. A block operation can thus be divisionally carried out.

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