Dual-port memory with read and read/write ports

Details Dual-port memory with read and read/write ports Dual-port memory with read and read/write ports

1992-01-31

1994-01-25

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Multiple port access

36518904, G11C 800

Patent

active

052821749

ABSTRACT:
A dual-port memory is accessed via a fast read port through p-channel access transistors and via a slow read/write port through n-channel access transistors. To reduce the disturbances resulting from a read operation through the read/write port, the row-line voltage applied to the gates of the n-channel access transistors is reduced to a value (e.g., 3 volts) below the value used for a write operation (e.g., 5 volts). In this manner, the lowered conductance of the n-channel access transistors during a read operation minimizes the effects of the pre-charged column conductors on the memory cell. Problems that could occur with a simultaneous read from the fast port, among others, are reduced.

REFERENCES:
patent: 5016214 (1991-05-01), Laymoun
patent: 5036491 (1991-07-01), Yamaguchi

Affiliated with

Also associated with

Rating

Dual-port memory with read and read/write ports does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual-port memory with read and read/write ports, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual-port memory with read and read/write ports will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-733179