Dual-port memory with inhibited random access during transfer cy

Details Dual-port memory with inhibited random access during transfer cy Dual-port memory with inhibited random access during transfer cy

1987-06-18

1990-01-30

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Serial read/write

365195, 365240, G11C 700

Patent

active

048978183

ABSTRACT:
In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

REFERENCES:
patent: 4322635 (1982-03-01), Redwine
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4535427 (1985-08-01), Jiang
patent: 4747081 (1988-05-01), Heilveil et al.

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