Dual port memory with asymmetric inputs and outputs, device,...

Details Dual port memory with asymmetric inputs and outputs, device,... Dual port memory with asymmetric inputs and outputs, device,...

2007-01-30

2007-01-30

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S308000

Reexamination Certificate

active

10925255

ABSTRACT:
An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width being different from the read bus width. A memory system including the asymmetric memory interface, memory controller and memory device is disclosed. The asymmetric nature of inputs and outputs reduces pin count by avoiding symmetric replication of bus widths for inputs and outputs. A method of accessing data in a memory device is also disclosed.

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