Dual port memory unit using a single port memory core

Details Dual port memory unit using a single port memory core Dual port memory unit using a single port memory core

2008-03-25

2008-03-25

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S233100, C365S230080

Reexamination Certificate

active

10906092

ABSTRACT:
A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the access request corresponding to the first port is processed in the high logic state of the memory clock cycle, and the access request corresponding to the second port is processed in the low logic state of the memory clock cycle. A single port memory core may provide multiple memory enable signals and corresponding strobe signals, with each combination of memory enable signal and strobe signal facilitating the memory access request from a corresponding port. An alternative embodiment uses the duration of each clock cycle of the memory clock signal more efficiently by starting the second memory access soon after completion of the first memory access (without waiting for the logic low of memory clock signal).

REFERENCES:
patent: 5398211 (1995-03-01), Willenz et al.
patent: 5781480 (1998-07-01), Nogle et al.
patent: 6629223 (2003-09-01), Bachot et al.
patent: 2005/0270853 (2005-12-01), Chiang et al.
patent: 2006/0098519 (2006-05-01), Kwon
“Dual Port Ram”, DS1609 from Dallas Semiconductor, pp. 1-7, Apr. 12, 2005.
S. K. Knapp, “XC4000 Series Edge-Triggered and Dual-Port RAM Capability”, XAPP 065 Jul. 2, 1996 (Version 1.0), pp. 1-4, from Xilinx, Inc. San Jose, CA, U.S.A.
“Bank-Switchable Dual-Ports”, Freqently Asked Questions , Application Note AN306, from IDT (Integrated Device Technology, Inc.)—Nov. 2003, pp. 1-5, Corporate Headquaters, Santa Clara CA.
Nick Sawyer and Marc Defossez, “Quad-Port Memories In Virtex Devices”, Application Note: Virtex, Spartan-II, Spartan-IIE, Virtex-E, Virtex-II, Virtex-II Pro Familles, from www.xilinx.com, XAPP228 (v1.0) Sep. 24, 2002, pp. 1-5, Xilinx, Inc. San Jose, CA, U.S.A.
“Implementing Multi-Port Memories in Axcelerator Devices”, Application Note, Jul. 2003, pp. 1-23 from http://www.actel.com , Actel Corporation, Sunnyvale, California.
“SR40 0.095—μm High—Speed Copper Standard cell/Gate Array ASIC”, Mar. 4, 2002, pp. 1-20 from http://www.ti.com/sc/docs/asic/prodinfo.htm: Texas Instruments Manual.
Viekko Koivumaa, “Implementing Shared Memory Interface with a TMS320C54x DSP”, Application Report SPRA505, Digital Signal Processing Solutions, Dec. 1998, pp. 1-8. from Texas Instruments.
“Dual Port Ram”, DS1609 from Dallas Semiconductor, pp. 1-7.

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