Computer graphics processing and selective visual display system – Computer graphics display memory system – Memory partitioning
Reexamination Certificate
1998-12-23
2001-08-07
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Memory partitioning
C345S531000, C345S565000, C348S715000, C348S718000
Reexamination Certificate
active
06271866
ABSTRACT:
FIELD OF THE INVENTION
This system relates generally to memory for raster scanned displays and, in particular, to a system for controlling the reading from and writing to dual-port memory used as a buffer for asynchronous digital video data to be displayed on an LCD display.
PROBLEM
Typically, a raster scanned display is synchronized to the incoming digital video to be displayed. When digital video is received for display on a raster scanned display device asynchronously with respect to the display frame read rate, the incoming video must be buffered. The video can then be read out of the buffer synchronously with respect to the display. The types of memory schemes typically employed for this buffering are described below, including dual-port memory, ‘ping-pong’ memory, and ‘ping-pong-pong’ memory configurations.
A dual-port (RAM) memory allows the simultaneous writing and reading of data. Dual-port memories simplify many data buffering schemes in that they do not require the complex multiplexing of address and data buses needed by memory configurations such as the ‘ping-pong’ and ‘ping-pong-pong’ buffering schemes (described below). However, in a typical system which uses a raster scanned video display device, such as an LCD display, the incoming video signal is asynchronous with respect to the display frame read rate. Therefore, absent some method of compensating for the difference in the read and write rates, the write and read addresses in video display memory must eventually cross each other. This crossover will occur because the incoming video data is filling a raster scanned video frame either faster or more slowly than the video frame display rate. When such address crossover occurs, the display device will display part of the new incoming video frame and part of the last incoming video frame. When the video image contains motion, this split becomes visible on the display, since part of the screen shows a segment of the image in the prior frame, and part of the screen shows a segment of the current image, which typically has moved relative to the prior frame. If the incoming video frame rate is close to the displayed frame rate, this frame split can remain static on the display for many frames or slowly move across the screen. Such a frame split may cause the displayed image to be significantly degraded in real-time applications such as flight navigation or monitoring of other time-critical functions.
A ‘ping-pong’ memory allows data to be written to a ‘ping’ buffer while data is read from a ‘pong’ buffer. At the completion of each frame, the ‘ping’ and ‘pong’ buffers are swapped. One of the problems with using this system with asynchronous reads and writes is similar in effect to that of a dual-port memory configuration. Since the incoming video frame is not matched to the video display read-out, the buffer swapping will cause part of an old frame to be displayed at the same time that part of a new frame is being displayed.
Similar to the ‘ping-pong’ memory arrangement described above, a ‘ping-pong-pong’ buffering scheme allows data to be written to a ‘ping’ buffer while data is read from either of two ‘pong’ buffers. When either the write or read operations are complete for a given frame, the operations then proceed to use the idle buffer for the next frame. This prevents the write and read addresses from ever crossing. Problems with this scheme include the added expense of having three banks of full field memory, the increased circuit board area used and the difficulty of multiplexing the address and data buses between the video input and output and the three banks of memory.
SOLUTION
The present invention overcomes the foregoing problems and achieves an advance in the art by providing a system which utilizes a ‘dual-port memory wrap-around’ scheme to seamlessly display video frames on a raster scanned display device, while avoiding the problems of address crossover, address and data multiplexing, and added cost and circuit board area.
In accordance with the present invention, video data to be displayed on a raster scanned display is written to and read from addresses in dual-port RAM memory, hereinafter referred to simply as LCD memory. Although the present invention is described in the context of an LCD-type display, the present system is functional with other types of raster display devices, such as plasma displays, field emission displays, or analog displays, such as CRTs. LCD memory is partitioned into a ‘single frame buffer’ having sufficient capacity to buffer a full LCD video frame, and an ‘extension buffer’ which is a contiguous extension of the single frame buffer. The two sections together comprise an ‘extended buffer’.
As long as the LCD memory write and read addresses are sufficiently separated by a predetermined number of lines N, video data is written and read using the single frame buffer for each frame. When the write and read addresses are closer than N lines, indicating that they are about to cross, wrap-around mode is initiated. Upon commencing wrap-around mode, the incoming video data for the next new frame is written using the ‘extended’ buffer, e.g., the write addresses continue to be incremented past the single frame buffer into the extension buffer. However, the video data continues to be read out only from the single frame buffer for one additional frame. When a frame write operation reaches the end of the extension buffer, the write operation for the current frame continues at the top of LCD memory. At the completion of this frame, the next frame write operation is again initiated immediately below the current frame ending. When the write location again reaches the end of the extension buffer, the writing ‘wraps’ back to the top of memory. After the LCD video read operation is completed for the one additional frame, the read operation uses the entire extended buffer, tracking the previous incoming video write addresses past the bottom of the last regular frame, into the extension buffer. This tracking continues for a predetermined number of frames Z, at which time the read and write addresses are compared. If, at the end of Z frames, the incoming video and LCD read-out frames are sufficiently out of synchronization, that is, if the write and read addresses are sufficiently spaced in LCD memory, the write and read operations go back to the normal single memory block mode beginning with their respective next new frame. If the write and read locations are still too close together, the above process is repeated. In this manner, the incoming video write address and the LCD video read-out address are prevented from crossing.
REFERENCES:
patent: 5130979 (1992-07-01), Ohtawa
patent: 5914711 (1999-06-01), Mangerson et al.
patent: 5949439 (1999-09-01), Ben-Yoseph et al.
patent: 5982397 (1999-11-01), Walsh
patent: 6012109 (2000-01-01), Schultz
Hancock William Ray
Quirk Robert John
Chauhan Ulka J.
Honeywell International , Inc.
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