Static information storage and retrieval – Addressing – Multiple port access
Patent
1991-09-04
1994-06-28
Popek, Joseph A.
Static information storage and retrieval
Addressing
Multiple port access
365156, 345150, G11C 700, G09G 128
Patent
active
053253388
ABSTRACT:
An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory. Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal. A second transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a bit line of the video path, and a gate coupled to a word line of the video path.
REFERENCES:
patent: 3728556 (1973-04-01), Arnell
patent: 3967252 (1976-06-01), Donnelly
patent: 4120048 (1978-10-01), Fuhrman
patent: 4140930 (1979-02-01), Tanaka
patent: 4216390 (1980-08-01), Stewart
patent: 4220997 (1980-09-01), Hager
patent: 4247791 (1981-01-01), Rovell
patent: 4310878 (1982-01-01), Hyatt
patent: 4394726 (1983-07-01), Kohl
patent: 4396976 (1983-08-01), Hyatt
patent: 4420819 (1983-12-01), Price et al.
patent: 4443855 (1984-04-01), Bishop et al.
patent: 4456965 (1984-06-01), Graber et al.
patent: 4471456 (1984-09-01), Branigan et al.
patent: 4485450 (1984-11-01), Charackus et al.
patent: 4490633 (1984-12-01), Noufer et al.
patent: 4507759 (1985-03-01), Yasui et al.
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4578780 (1986-03-01), Baba
patent: 4627018 (1986-02-01), Trust et al.
patent: 4684942 (1987-08-01), Nishi et al.
patent: 4715017 (1987-12-01), Iwahashi et al.
patent: 4719596 (1988-01-01), Bernstein et al.
patent: 4768172 (1988-08-01), Sasaki
patent: 4780852 (1988-10-01), Kawigaya et al.
patent: 4791607 (1988-12-01), Igarashi et al.
patent: 4815033 (1989-03-01), Harris
patent: 4905189 (1990-02-01), Brunolli
patent: 5027008 (1991-06-01), Runaldwe
patent: 5036492 (1991-07-01), Runaldwe
patent: 5150326 (1992-09-01), Aoki
Brooktree Corp., "Bt 451, Bt457, Bt458 125 MHz/170 MHz Monolithic CMOS 256 Color Palette RAMDAC", 1989.
Baitinger, et al., "Monolithic Storage Cell with FETs," 1972, vol. 14, No. 12, IBM Technical Disclosure Bulletin.
Boysel, et al., "Multiphase Clocking Achieves 100-Nsec MDS Memory," 1968, EDN.
Glasser, et al., "Random Access Memory," 1985, The Design and Analysis of VLSI Circuits, Chap. 7, pp. 388-393, 422-423.
Gray, et al., "Analog MOS Integrated Circuits," 1978, IEEE J. Solid-State Circuits, vol. SC-13, pp. 1-49.
Gray, et al., "Analysis and Design of Analog Integrated Circuits," 2d Ed., 1984, pp. ix-xiii, 703-764.
Hardee, et al., "THPM 15.2: A 30ns 64k CMOS RAM," 1984, IEEE Int'l Solid-State Circuits Conference, pp. 216-217, 341.
Intel Corp., "Circuit Contained in the Am 80286 Database," 1984.
Ishimoto, et al., "WAM 3.1: A 256k Dual Port Memory," 1985.
IEEE Intl. Solid-State Circuits Conference, pp. 38-39, 300.
Pinkham, et al., "A High Speed Dual Port Memory with Simultaneous IEEE J. of Solid-State Circuits, Serial & Random Mode Access for Video Apps.," pp. 999-1007.
Pinkham, "Video Memory Technology and Applications," 1984, Wescon/'84 Conference Record, pp. 29/5 1-9.
Pope, "Asynchronous Dual-Post RAM Simplifies Multiprocessor Systems," 1983, Electrical Design News, vol. 28, No. 18, pp. 147-154.
Takahashi, et al., "A 240k Transistor CMOS Array with Flexible Allocation of Memory and Channels," 1985, IEEE J. of Solid-State Circuits, vol. SC-20, No. 5, pp. 1012-1017.
Kodata, et al., "An 84b Content Addressable and Reentrant Memory," 1985, ISSCC Digest of Technical Papers, pp. 42-43.
Haraszti, "A Novel Associative Approach for Fault-Tolerant MOS RAM's," 1982, IEEE J. of Solid-State Circuits, vol. SC-17, No. 3, pp. 539-546.
Nikaido, et al., "A 1K Bit Associative Memory LSI," 1983, Japanese Journal of Applied Physics, vol. 22, pp. 51-54.
Reinert, et al., "A 32.times.9 ECL Dual Address Register Using an Interleaving Cell Technique," ISSCC Digest of Technical Papers, 1977, pp. 72-74.
Synertek, "Sy2130/Sy2131 1024.times.8 Dual Port Random Access Memory," 1984, pp. 1-31.
Chester, "A 1-Micron CMOS 128 MHz Video Serializer Palette, Etc.", 1989, IEEE Comput. Sec. Press, CAT. No. 89CH2704-5, p. 1/117.
Conner, "Color-Palette Chips Bundle Extra Features with RAM Lock-up Table and DACs," 1988, EDN vol. 33, No. 20, pp. 67-76.
Yeung, et al., "A 300 MHz Bipolar-CMOS Video Shift Register with FIFO," 1987, ISSCC Digest of Technical Papers, pp. 56-57.
Plants William
Runaldue Thomas J.
Advanced Micro Devices , Inc.
Popek Joseph A.
LandOfFree
Dual port memory, such as used in color lookup tables for video does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual port memory, such as used in color lookup tables for video , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual port memory, such as used in color lookup tables for video will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2381988