Excavating
Patent
1994-08-25
1996-11-26
Beausoliel, Robert W.
Excavating
371 211, 371 213, G01R 1512, G11C 2900
Patent
active
055793223
ABSTRACT:
An object of the present invention is to provide an embedded testing circuit of a dual port memory capable of effectively testing the memory using a short test pattern while making simultaneous write/read from both of the ports.
The testing circuit comprises an address inputting circuit selectively supplying M-sequence pattern data or their inverted pattern data to scan registers on the port A at the address input side and also selectively supplying pattern data in inverse relationship to the pattern data supplied to the port A to scan registers on the port B and a data inputting circuit selectively supplying the M-sequence pattern data or their inverted pattern data passed through the scan registers on the port A at the address input side to scan registers on the port A at the data input side and also selectively supplying the inverted pattern data or the M-sequence pattern data passed through the scan registers on the port B at the address input side to scan registers on the port B at the data input side.
REFERENCES:
patent: 3961252 (1976-06-01), Eichelberger
patent: 5040150 (1991-08-01), Naitoh et al.
patent: 5222067 (1993-06-01), Hiroshi
Conference Paper; Built-in Self Test in Multi-Post RAMS Castro, A. V.; Nicolaidis, M; Lestrat, P; Courtois, B. 1991 IEEE International Conference on Computer aided Design pp. 248-251.
"Built-in self test for Multi-port Rams" by V. Castro Alves, M. Nicolaidis, P. Lestrat and B. Courtois.
Beausoliel Robert W.
Iqbal Nadeem
Kananen Ronald P.
Sony Corporation
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