Dual-port memory controller for adjusting data access timing

Details Dual-port memory controller for adjusting data access timing Dual-port memory controller for adjusting data access timing

2005-08-23

2005-08-23

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S149000, C711S152000

Reexamination Certificate

active

06934824

ABSTRACT:
A dual-port memory controller having a memory controller and at least one delaying unit. Since the memory controller executes a data access by selecting one processor, the memory controller outputs at least one request disapproval signal indicating that it cannot accept data access requests from other processors. The delaying unit includes a clock oscillator, and flip-flops receiving the clock signal and delaying the request disapproval signal. The delaying unit varies the delay time by varying the clock frequency of the clock oscillator. The memory controller executes data access to the same memory area after a predetermined period of time elapses, so processors can read/write stabilized data.

REFERENCES:
patent: 6233659 (2001-05-01), Cohen et al.
patent: 6334174 (2001-12-01), Delp et al.
patent: 6370067 (2002-04-01), Ko et al.
patent: 6557085 (2003-04-01), Mattausch
patent: 6625699 (2003-09-01), Cohen et al.

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