Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2007-10-23
2007-10-23
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Addressing
Multiple port access
C365S063000, C365S154000
Reexamination Certificate
active
11403370
ABSTRACT:
A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to reduce one or both of stray and coupling capacitance associated with the bit lines. In one exemplary embodiment, the bit lines from each port that are in closer proximity to the bit lines of the other (or another) port are disposed in different metallization layers to reduce coupling capacitance therebetween. One or more further embodiments can include VSSor VDDline(s) located horizontally between the bit lines and metal to substrate contacts for the bit lines can be formed in opposite corners of the memory device to further reduce capacitance.
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Huang Pao-Lu Louis
Lien Chuen-Der
Auduong Gene N.
Finnegan & Henderson et al.
Integrated Device Technology Inc.
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