Dual-port memory

Details Dual-port memory Dual-port memory

1996-05-06

1999-08-31

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Multiple port access

365203, 365210, G11C 700

Patent

active

059462612

ABSTRACT:
A dual-port memory includes a dummy memory cell associated with a dummy output line and with a precharge transistor, the output of the dummy cell being at "0". A dummy read transistor is turned on by the active state of the read selection signal and connects the output of the dummy cell to the dummy output line. Circuitry is provided for turning on the output transistors of the memory when the state of the dummy output line reaches a predetermined switching threshold of an inverter.

REFERENCES:
patent: 4849935 (1989-07-01), Miyazawa
patent: 4864543 (1989-09-01), Ward et al.
patent: 5245575 (1993-09-01), Sasaki et al.
patent: 5268869 (1993-12-01), Ferris et al.
patent: 5317537 (1994-05-01), Shinagawa et al.
patent: 5424995 (1995-06-01), Miyazaki et al.
Proceedings of the IEEE 1989 Custom Integrated Circuits Conference, May 15, 1989, San Diego, CA, pp. 23.4.1-23.4.4, Kawauchi, et al., "A 1.0um Compilable FIFO Buffer for Standard Cell".
1990 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 7, 1990, Honolulu, HI, pp. 65-66, Sakaue, et al., "A 0.8um BiCMOS ATM Switch on the 800Mbps asynchronous buffered banyan network".

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