Dual-port buffer-to-memory interface

Details Dual-port buffer-to-memory interface Dual-port buffer-to-memory interface

2000-10-03

2004-05-25

Padmanabhan, Mano (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S005000, C711S165000, C710S307000, C365S230050

Reexamination Certificate

active

06742098

ABSTRACT:

FIELD OF THE INVENTION
This present invention relates generally to digital memory devices and systems, and more particularly to memory module architectures and methods for operating such devices and systems.
BACKGROUND OF THE INVENTION
Microprocessors, digital signal processors, video devices, and many other types of digital data processing devices rely on an attached high-speed memory system to hold data and/or processor instructions needed by the processing device. As these processing devices become faster and more powerful, the increased demands placed on them generally translates to a need for larger and faster attached memory systems.
FIG. 1
depicts a typical memory system configuration. One or more memory devices
26
AA,
26
AB,
26
BA,
26
BB,
26
CA, and
26
CB interface with a memory controller
20
through memory bus
22
. A host (e.g., a central processing unit (CPU), not shown) also connects to memory controller
20
through a front-side bus FSB. The memory devices hold data in arrays of addressable memory cells. Memory controller
20
controls the exchange of data between the host and the memory storage devices.
Memory bus
22
carries memory signals on a collection of signal lines. Memory signals fall generally into one of several categories including clock and control signals, address signals, command signals, and data signals. Data signals carry the actual data that will be stored in, or retrieved from, a memory device. Address signals specify the location within a memory device where data is to be read from or written to, and may also select which of several memory devices is to be accessed. Command signals instruct a memory device as to what type of operation is to be performed, e.g., read, write, refresh, and possibly as to which of several access modes (such as a burst mode) should be used for a data transfer. Clock and control signals synchronize the other signals passing between controller
20
and the memory devices. Although memory bus
22
may use a separate signal line for each memory signal (e.g., 32 address lines to transfer a 32-bit-wide address in one clock cycle and 32 data lines to transfer a 32-bit-wide data word in one clock cycle), various schemes also exist to re-use one or more signal lines for different memory signals during different clock cycles of a memory transaction.
In the configuration shown in
FIG. 1
, memory bus
22
is a multi-drop memory bus. In other words, bus
22
is arranged with a backbone of signal lines. A signal line stub, or “drop”, connects each of the memory devices (e.g.,
26
A) to the backbone. Typically, memory bus
22
will comprise a collection of leads routed on a printed circuit board
21
known as the “main board” or “motherboard”. Memory controller
20
mounts to motherboard
21
and connects to one end of the leads comprising memory bus
22
. Each drop of memory bus
22
connects to an electrical terminator, or socket. A typical main board contains multiple memory sockets, e.g., the three sockets
28
A,
28
B, and
28
C shown in FIG.
1
.
Memory is added to the memory system by inserting memory modules (e.g.,
24
A,
24
B,
24
C) into one or more of the sockets. One popular type of memory module is a Dual In-line Memory Module, or DIMM. The DIMM is a rectangular low-profile circuit board that has electrical contact points arranged on both sides along one long edge. The contact points form electrical connections to the main board's memory bus when the DIMM is inserted into a DIMM memory socket.
A DIMM generally has multiple individual memory devices mounted to it. The devices all work in parallel to perform memory functions. For instance, a DIMM may have eight memory devices, each of which receives the same memory address from the controller. If the size of a data word is 32 bits, each of the memory devices is responsible for four bits of the data word that is placed on the memory bus.
Some DIMM designs (like the design shown in
FIG. 1
) have more than one bank of memory devices. For example,
FIG. 2
shows a block diagram of a registered DIMM
24
containing eighteen memory devices arranged in two banks, one bank containing devices D
00
-D
08
and the other containing devices D
10
-D
18
. In a registered DIMM, the system clock CK
0
is received by phase-locked-loop (PLL)
27
, which creates a set of module clock signals. Address and command signals ADD/CMD are latched into a register
25
at the edge of one clock cycle, and then redriven onto the module addressing/command bus as register signals RADD/RCMD on the following clock cycle. Note that two bank select signals, B
0
_SEL# and B
1
_SEL#, each pass through register
25
and connect to a chip select pin on a corresponding one of the banks of memory devices. The data lines DQ of the memory device banks each connect to the memory bus of the host system. A total of nB DQ lines carry data signals, where B is the number of devices in one bank (e.g., eight or nine), and n is the data width of each device (e.g., four, eight, or sixteen bits). In addition, B DQS lines carry data strobes (one per device). The DQS data strobes travel with the data signals, and can be used for source-synchronous clocking of the data signals at the receiver.
FIG. 3
shows a timing diagram for two consecutive random reads to memory bank D
00
-D
08
. At TI, the memory controller transmits an ACTIVE command along with a ROW address, and takes B
0
_SEL# low to select bank
0
on module
24
. Register
25
latches these signals, and places them on the module bus at T
2
. After a known RAS (row address strobe) latency, the controller transmits a READ command along with a COL “a” address. These signals also pass through register
25
with a one-clock cycle delay. After a known CAS (column address strobe) latency, the memory bank places data (DO a) from ROW and COL “a” onto bus lines DQ, and DQS is driven as well. Note that a read to a COL “b” can immediately follow the first read, as the columns are on the same ROW.


REFERENCES:
patent: 5815646 (1998-09-01), Purcell et al.
patent: 5825424 (1998-10-01), Canfield et al.
patent: 5935232 (1999-08-01), Lambrecht et al.
patent: 6034878 (2000-03-01), Osaka et al.
patent: 6141739 (2000-10-01), Provence et al.
patent: 6480947 (2002-11-01), Hasegawa et al.
patent: 6530033 (2003-03-01), Raynham et al.

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