Dual-PLL signaling for maintaining synchronization in a...

Details Dual-PLL signaling for maintaining synchronization in a... Dual-PLL signaling for maintaining synchronization in a...

2004-10-19

2009-12-08

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S147000

Reexamination Certificate

active

07630468

ABSTRACT:
A communications management system introduces a low bandwidth phase locked loop (LoBW-PLL) working in tandem with a high bandwidth phase locked loop (HiBW-PLL). The LoBW-PLL only needs to follow the average frequency of the transported clock and not all of the excursions made by the master clock. During periods of downstream outage, the LoBW-PLL opens its loop and free wheels such that disturbances caused by a reacquisition do not impact the concept of time for the LoBW-PLL. After reacquisition, the LoBW-PLL and HiBW-PLL are compared to determine if a timing error has occurred. If a timing error is detected, the magnitude of the timing error is measured upon completion of the reacquisition cycle, and this measurement is used to correct the timing error.

REFERENCES:
patent: 5652532 (1997-07-01), Yamaguchi
patent: 5856762 (1999-01-01), Werker et al.
patent: 6483885 (2002-11-01), Bradley et al.
patent: 2002/0001359 (2002-01-01), Skierszkan et al.
patent: 2002/0027966 (2002-03-01), Fukuhara
patent: 2005/0111605 (2005-05-01), Loke et al.

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