Dual-packed capacitor DRAM cell structure

Details Dual-packed capacitor DRAM cell structure Dual-packed capacitor DRAM cell structure

1996-10-25

1999-02-23

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257306, 438244, H01L 2976, H01L 2994, H01L 27108, H01L 31119

Patent

active

058747575

ABSTRACT:
A dual-packed capacitor DRAM structure includes a semiconductor substrate having a surface with a trench disposed therein, the trench having a bottom and side walls. An insulating layer covers the bottom and side walls inside the trench and covers part of the semiconductor substrate surface adjacent the trench. A pair of pass transistors are disposed symmetrically on opposite sides of the trench in the semiconductor substrate. Each pass transistor includes a gate, a source region and a drain region, the respective drain regions of the pass transistors being disposed nearest the trench. A first storage electrode is disposed above the insulating layer inside the trench and electrically coupled to the drain region of a first one of the pair of pass transistors. A first dielectric layer is disposed above a surface of the first storage electrode. A common opposed electrode is disposed above the first dielectric layer and has a vertical main section extending into the trench, a horizontal main plate extending parallel to the substrate surface, and at least one extended section extending from the horizontal main plate perpendicular to the substrate surface. The first storage electrode, the first dielectric layer and a lower portion of the common opposed electrode together make up a first capacitor structure. A second dielectric layer is disposed above the common opposed electrode, and a second storage electrode is disposed above the second dielectric layer and electrically coupled to the drain region of a second one of the pair of pass transistors. The second storage electrode, the second dielectric layer and an upper portion of the common opposed electrode together make up a second capacitor structure,

REFERENCES:
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5089869 (1992-02-01), Matsuo et al.
patent: 5102820 (1992-04-01), Chiba
patent: 5126810 (1992-06-01), Gotou
patent: 5142639 (1992-08-01), Kohyama et al.
patent: 5155657 (1992-10-01), Oehrlein et al.
patent: 5158905 (1992-10-01), Ahn
patent: 5164337 (1992-11-01), Ogawa et al.
patent: 5172201 (1992-12-01), Suizu
patent: 5196365 (1993-03-01), Gotou
patent: 5206787 (1993-04-01), Fujioka
patent: 5227322 (1993-07-01), Ko et al.
patent: 5266512 (1993-11-01), Kirsch
patent: 5274258 (1993-12-01), Ahn
patent: 5336912 (1994-08-01), Ohtsuki
patent: 5338955 (1994-08-01), Tamura et al.
patent: 5354701 (1994-10-01), Chao
patent: 5354704 (1994-10-01), Yang et al.
patent: 5371701 (1994-12-01), Lee et al.
patent: 5389568 (1995-02-01), Yun
patent: 5438011 (1995-08-01), Blalock et al.
patent: 5442212 (1995-08-01), Eimori
patent: 5443993 (1995-08-01), Park et al.
patent: 5459095 (1995-10-01), Huang et al.
patent: 5460996 (1995-10-01), Ryou
patent: 5478768 (1995-12-01), Iwasa
patent: 5478770 (1995-12-01), Kim
patent: 5482886 (1996-01-01), Park et al.
patent: 5508222 (1996-04-01), Sakao
patent: 5523542 (1996-06-01), Chen et al.
patent: 5543346 (1996-08-01), Keum et al.
patent: 5550080 (1996-08-01), Kim
patent: 5561309 (1996-10-01), Cho et al.
patent: 5561310 (1996-10-01), Woo et al.
patent: 5572053 (1996-11-01), Ema
patent: 5595931 (1997-01-01), Kim
"Mini-Trenches in Polysilicon For Dram Storage Capacitance Enhancement", IBM Technical Disclosure Bulletin, vol. 33, No. 9, Feb. 1991.
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS", International Electron Devices Meeting, pp. 592-595, Dec. 1988.
Wakamiya et al., "Novel Stacked Capacitor Cell for 64-Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical papers, pp. 69-70.

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