Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-03
2004-05-25
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S326000, C257S336000, C257S344000, C257S408000, C438S216000, C438S261000, C438S287000, C438S591000, C438S981000
Reexamination Certificate
active
06740944
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly, to a design of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), which have reduced leakage currents, and to a method for fabricating the same.
BACKGROUND OF THE INVENTION
FIG. 1A
depicts a partial top-view of a conventional MOSFET device
10
. As shown in
FIG. 1A
, MOSFET device has a gate
12
over a substrate
22
. A source region
14
and a drain region
16
are located in substrate
22
on opposite sides of gate
12
. Source and drain regions
14
and
16
are commonly referred to as having a length L that extends in the y-direction and a width W that extends in the z-direction, shown in FIG.
1
A. Consistent with that usage, the dimension of a MOSFET gate, such as gate
12
, in the z-direction, will hereafter be referred to as its width, and a reference to the ends of the gate will be understood to refer to opposite ends of the gate in the z-direction.
FIG. 1B
is a cross-sectional schematic view of the MOSFET device
10
. As shown in
FIG. 1B
, source
14
and drain
16
are formed in a well region
20
in substrate
22
. Gate
12
is separated from substrate
22
and thus source
14
and drain
16
by an oxide layer
15
. The thickness of oxide layer
15
and the degree of any overlap of the gate over the source and the drain regions can vary. Device
10
may also have dielectric spacers
50
and
55
on two sides of gate
12
, and lightly doped drain (LDD) regions
40
and
42
adjacent source and drain regions
14
and
16
, respectively. Spacers
50
and
55
help to farther isolate gate
12
from source
14
and drain
16
to prevent the build-up of device capacitance. Device
10
may be isolated from other devices also formed on substrate
22
by dielectric trenches (not shown) at some or all sides of device
10
.
Source and drain regions
14
and
16
in substrate
22
are typically regions doped with dopants of a same conductivity type. Well region
20
is typically doped with dopants of a different conductivity type from that in the source and drain regions. LDD regions
40
and
42
are typically doped with dopants of the same conductivity type as in the source and drain regions, but dopant concentrations in the LDD regions are typically much lighter than in the source and drain regions.
A MOSFET device, such as device
10
, behaves like a switche: when it is “on”, i.e., when a sufficient threshold voltage, V
t
, is applied to the gate, a channel
18
is formed in a region immediately under oxide layer
15
and relatively large currents flow through the channel between the source and drain. Ideally, when the MOSFET
10
is “off”, there is no current flow. In practice, however, there is typically a small amount of unwanted leakage current when device
10
is off. Assuming that I
on
is the current that flows between the source and drain of a MOSFET device in the “on” state, and I
off
is the small amount of unwanted leakage current that flows or “leaks” between any two of the source, drain and gate in an off-state of the device, the on/off ratio (I
on
/I
off
) of a transistor is a common figure of merit and benchmark for transistor performance comparisons. Higher I
off
values result in lower on/off ratios, and indicate degraded transistor performance.
There are several causes of off-state leakage currents. Parasitic leakage paths between the gate and channel, commonly referred to as sidewall leakage, can result in excessive forward and reverse gate leakage currents. For example, leakage can occur where the gate overlaps or is closely adjacent the drain and the source (commonly referred to as edge conduction leakage). Devices which exhibit high edge conduction and sidewall leakage are characterized by degraded device performance, such as increased off-state power dissipation.
Leakage currents can also result from other sources within a semiconductor device or as a consequence of various device processing steps. For example, in practice processing steps associated with the formation of shallow trench isolation (STI) may result in electrons being trapped near a substrate-nitride interface, inducing sidewall leakage between an isolating trench and a device.
Leakage currents can also occur due to inverse narrow width effect (INWE). INWE is a parasitic phenomenon which lowers the effective threshold voltage as the length of the gate becomes smaller. Device performance, reliability, layout efficiency and yield are known to be degraded by the inverse narrow width effect. The lower threshold voltage, V
t
, means higher off-state leakage currents that increase overall power consumption, result in excess heat generation and can cause problems related to the dissipation of excess heat.
Another design and manufacturing concern relates to gate oxide thinning. Gate oxide thinning occurs over the device lifetime due to stresses on the device such as high applied voltage levels, temperature and imperfections in the oxide layer. The phenomenon of the thinning of the gate oxide film increases the likelihood of dielectric breakdown which can adversely affect the operating characteristics of devices. Moreover, the well-known “hot-carrier effect” can cause damage to the oxide layer by increasing the chances of oxide breakdown, particularly at oxide edges.
As device geometries continue to shrink and threshold voltages continue to scale down, leakage currents have an even greater impact on device performance. Particularly in low power or high temperature applications, leakage currents can represent a significant source of device degradation and performance impairment. The problem of leakage currents is exacerbated by the existence of numerous possible causes of such currents. To resolve the problem requires complex failure identification and analysis. Such failure analysis projects are costly and highly dependent upon the skills and resourcefulness of the individuals conducting the failure analysis. Therefore, a need exists for a device design and fabrication approach that can compensate for manufacturing defects, device degradation or tolerance failures due to leakage currents.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a design of a MOS transistor with reduced leakage current and without adverse device performance that typically accompanies other prior art approaches.
In one embodiment of the present invention, a MOSFET has a thicker gate oxide at one or more ends of the gate, thereby minimizing leakage currents without adversely impacting overall device V
t
as would occur if the gate oxide were made uniformly thicker.
The present invention also includes a method for fabricating a MOS transistor where the gate oxide is thicker at the ends of the gate for the purposes of reducing off-state leakage, increasing reliability and enhancing overall device performance. In one embodiment of the present invention, the MOS transistor is fabricated on a semiconductor substrate together with other devices in an integrated circuit (IC), using conventional IC fabrication steps. With some modification of one or more masks in the conventional IC processing steps, a nonuniform gate oxide is created that is thicker near the ends of the conducting channel of MOS transistor. Therefore, the present invention provides a MOS transistor with reduced leakage currents, and does not require additional complicated manufacturing steps for making the MOS transistor.
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Fung, S., Chan, M., Ko, P., “Inverse-Narrow-Width Effect of Deep Sub-Micrometer Mosfets with Locos Isolation,” Received Oct. 8
Liu Yowjuang (Bill)
McElheny Peter John
Altera Corporation
Huynh Andy
Morgan & Lewis & Bockius, LLP
Nelms David
LandOfFree
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