Dual operation mode memory device

Details Dual operation mode memory device Dual operation mode memory device

2007-02-06

2007-02-06

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230010

Reexamination Certificate

active

11104136

ABSTRACT:
Disclosed is a memory device, which combines a self-refresh enable signal and a power mode decision signal and prevents an internal voltage from being dropped down without the increase of IDD3P current when the memory device performs a self-refresh operation. The memory device includes an operation mode internal voltage generator used in an operation mode, and a controller for enabling the operation mode internal voltage generator while performing a self-refresh operation with a predetermined period and activating a memory cell array of the memory device, even when the memory device is in a stand-by mode.

REFERENCES:
patent: 6487136 (2002-11-01), Hidaka
patent: 6515928 (2003-02-01), Sato et al.
patent: 2004/0027888 (2004-02-01), Kurita
patent: 2005/0018568 (2005-01-01), Tsuda et al.
patent: 2005/0117432 (2005-06-01), Graaff et al.

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