Dual on-chip and in-package clock distribution system

Details Dual on-chip and in-package clock distribution system Dual on-chip and in-package clock distribution system

1999-12-08

2002-10-08

Butler, Dennis M. (Department: 2185)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S503000

Reexamination Certificate

active

06463547

ABSTRACT:

BACKGROUND OF THE INVENTION
Accurate clock distribution, especially in microprocessors, is typically the criticality at high clock speeds. The operation of logic on physically remote sections of the chip must be coordinated to ensure collective proper operation. Even with careful design, however, problems still arise due to on-chip process, temperature, power supply, and other variations .
Active skew management of clock domains, commonly included in the form of Delay Locked Loops (DLL) or Phase Locked Loops (PLL), can reduce some of the variation problems within the separate clock domains. The clock domains may be widely dispersed across the die but must receive a synchronous clock signal, or timing reference, the origin of which may be remote from the clock domain. For a processor with clock domains, the receivers may be the phase detector of a DLL or PLL, or it may be an inverter that designates the start of the local clock distribution network.
If the clock timing reference is distributed on the die, signal attenuation requires repeater (i.e. inverter) insertion at regularly spaced intervals between the source and receivers. Modem microprocessors are too large to send a signal across the die without several repeaters. The problem with this approach is that widely dispersed repeaters will be subject to process, voltage, and temperature variations, and the interconnect may inductively or capacitively couple to the signals causing signal delay variation. These variations can cause race-through failure if not corrected. Race-through failure is a functional failure caused by a signal propagating through two latches (instead of one) on a single clock edge. Even if race-though failure is prevented by deskewing techniques, clock edge variation will inevitably cause chip performance degradation.
Alternatively, the timing reference may be sent through the package. The generally preferred approach to in-package distribution is to drive the clock off the chip through a package layers to re-enter the chip through bumps near each receiver. The advantage of this approach is that the package interconnect is typically several orders of magnitude less lossy than on-chip interconnect. That is, in-package interconnect can be more than 100 times less resistive. This allows the clock timing reference to be distributed without repeaters.
SUMMARY OF THE INVENTION
The primary disadvantage of in-package clock distribution is that wafer probe testing is very difficult and potentially costly. Wafer probe testing is a set of low-frequency tests to determine which chips are to be discarded prior to packaging. The tester must be able to emulate the package layer dedicated to the clock distribution, or else provide a carefully synchronized clock signal to all clock-domain receivers. If the clock is not synchronized to all receivers, functional race-through failure is likely (if no other precautions are taken). Such testing failures prevent accurate assessment of the chip.
Chip size increases have been a consistent trend for many years in microprocessor design. This trend, thus, renders on-chip clock distribution even more problematic. This, coupled with process shrinks, has made clock distribution an increasingly difficult problem for each design phase.
The present invention is directed to a clock distribution system for a semiconductor device which provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.
In general, according to one aspect, the invention features a clock distribution system for a packaged semiconductor device. The system comprises an on-chip clock distribution network that transmits a clock signal between a clock source and clocked logic. An in-package clock distribution network also transmits the clock signal between the source and logic. A mode selector is provided that supplies the clock signal, from either the on-chip clock distribution network or the in-package clock distribution network, to the clocked logic.
In specific embodiments, the mode selector disables the on-chip distribution network during normal operation of the packaged semiconductor device. Normal operation typically occurs when the device is installed on a printed circuit board, such as a motherboard of a computer system. The mode selector, however, provides only the clock signal received via the on-chip distribution network when the semiconductor device is being tested by a probe tester, for example. Typically, this testing occurs prior to installation of the chip in the package.
Preferably, the mode selector comprises a clock source demultiplexer. This demultiplexer is located near the clock source for the chip. It provides the clock signal on either the on-chip clock distribution network or the in-package clock distribution network. Logic multiplexers are also provided, which are located near the clock logic on the chip. It provides the clock signal from either the on-chip clock distribution network or the in-package clock distribution network to the clocked logic.
In general, according to another aspect, the invention also features a clock distribution method for a packaged semiconductor device. This method comprises distributing a clock signal via an on-chip clock distribution network from a clock source to clocked logic during testing and providing for this clock distribution. During normal operation, however, when the chip is packaged, the clock signal is distributed by an in-package clock distribution network from the clock source to the clocked logic.
The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.


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Cao, L., et al., “A Novel ‘Double-Decker’ Flip-Chip/BGA Package for Low Power Giga-Hertz Clock Distribution”,Electronic Components and Technology Conference, pp. 1152-1157 (1997).
Zhu, Q., et al., “Planar Clock Routing for High Performance Chip and Package Co-Design”,IEEE Transactions on Very Large Scale Integration(VLSI)Systems, vol. 4, No. 2, pp. 210-225 (Jun. 1996).
Zhu, Q., et al., “Package Clock Distribution Design Optimization for High-Speed and Low-Power VLSI's”,IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, vol. 20, No. 1, pp. 56-63 (Feb. 1997).
Zhu, Q., et al., “Chip and Package Co-Design Technique for Clock Networks”,Multi-Chip Module Conference, pp. 160-163 (1996).

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