Dual numerically controlled delay logic for DQS gating

Details Dual numerically controlled delay logic for DQS gating Dual numerically controlled delay logic for DQS gating

2007-11-20

2007-11-20

Nguyen, Tanh Q (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Flow controlling

C710S005000, C710S036000, C711S100000, C711S105000, C711S154000, C711S167000, C713S400000, C713S401000

Reexamination Certificate

active

10600247

ABSTRACT:
Presented herein is a scheme for reducing the likelihood of erroneous DQS signals. Logic is incorporated proximate to a memory controller and receives a signal indicating a read request and a DQS signal from a memory module. The logic transmits a signal indicating the presence of data, based on the timing relationship between the DQS signals and signal indicating read requests.

REFERENCES:
patent: 6445642 (2002-09-01), Murakami
patent: 6498766 (2002-12-01), Lee et al.
patent: 6657634 (2003-12-01), Sinclair et al.
patent: 6763416 (2004-07-01), LaBerge
patent: 6820181 (2004-11-01), Jeddeloh et al.

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