Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-10-20
2004-03-23
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S100000, C710S310000, C710S316000, C711S115000, C711S133000, C711S154000, C711S212000, C714S724000
Reexamination Certificate
active
06711646
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
The application is related to a new utility patent application Ser. No. 09/693,331, concurrently filed herewith entitled, “Dual Mode (Registered/Unbuffered) Memory Interface Cost Reduction”.
BACKGROUND OF THE INVENTION
In order to execute software programs, most microprocessors require at least some random access memory (RAM). The amount of RAM required by the program is dependent on the nature and complexity of the software application being processed. RAM is contained in discrete memory integrated circuits (ICs).
The RAM ICs are connected to the microprocessor through electrical connections called “nets” (also referred to as wires or traces). The amount of RAM available within a single memory IC is limited by the available manufacturing process technology. Thus, as more RAM is required, more memory ICs must be used.
Further, the microprocessor is electrically limited by the available process technology. This electrical limitation is in the maximum number of devices that can be connected to one of the microprocessor's signal pins. Specifically, each pin presents a capacitive load based on the components attached to it via an electrical net and there is a limit on the maximum capacitive load that can be driven by a signal pin. In certain cases, it is possible that the number of devices required by a microprocessor, in order to provide sufficient RAM, can exceed the number of devices that microprocessor can electrically access.
Generally, if the capacitive load is too high for the microprocessor to manage, an external device called a buffer or register is placed between the microprocessor and the memory ICs. The external buffer or register is designed to handle the higher capacitive load. Those skilled in the art will recognize that registers are distinct from buffers, and whether a buffer or register is used depends on the memory technology being used.
When an external register or buffer is used, an additional delay in the signal path is added, i.e., the maximum rate at which the memory devices can be accessed is slowed down. For higher performance, it is more desirable to use an unbuffered interface, i.e., an interface without any external buffers or registers. However, as discussed above, the combination of total memory requirement and the amount of memory available per device may require the use of a buffered or registered interface.
Also, it is often desirable to provide a microprocessor the use of both unbuffered and registered/buffered memory within the same system. However, in a situation where memory is located on a separate module attached to a microprocessor through a connector and several connectors are available for “memory expansion,” a microprocessor may not be able to access a block of unbuffered memory on another module. This results in the requirement that all modules be of the same configuration, either registered/buffered or unbuffered.
Further, when systems having small amounts of unbuffered memory are upgraded to a larger amount of memory that must be registered, e.g., because of the capacitive load created, the unbuffered memory becomes unusable to the microprocessor. As a result, the existing and still functional memory cannot be used. Thus, not only must the desired increased in capacity be purchased, but also replacements for the existing and now unusable memory must be purchased.
Referring to
FIG. 1
, in a typical computer system, a microprocessor (
10
) is connected to unbuffered RAM (
12
) and (
14
) via electrical nets (
20
). Also, or alternatively, microprocessor (
10
) is connected to registered/buffered RAM (
18
) via electrical net (
20
) which passes through register/buffer (
16
). As discussed above, those skilled in the art will appreciate that whether a register or a buffer is used is dependent on the memory technology employed.
SUMMARY OF THE INVENTION
In one aspect, a dual mode memory interface comprises a bus switch and a register/buffer operatively coupled to the bus switch. The dual mode memory interface may comprise enable/disable pins operatively coupled to the bus switch and the register/buffer, wherein the enable/disable pins are configured so that only one of the bus switch and the register/buffer is active at a time. The bus switch may be a transistor configured as a pass gate. The dual mode memory interface may be implemented in a single integrated circuit package. The dual mode memory interface may further comprise a system controller for detecting a type of memory module connected to the dual mode memory interface and enabling one of the bus switch and register/buffer based on the type of memory module detected.
In one aspect, a method of interfacing a memory module with a microprocessor comprises switching between unbuffered and registered/buffered mode based on the memory module being interfaced with the microprocessor. The method may further comprise detecting a type of memory module connected to the dual mode memory interface and switching between unbuffered and registered/buffered mode based on the type of memory module detected. The method may further comprise enabling one of a bus switch and register/buffer based on the type of memory module detected.
In one aspect, a dual mode memory interface comprises means for detecting a type of a memory and means for switching between unbuffered registered/buffered modes based on the type of the memory detected.
In one aspect, an apparatus for interfacing a memory module with a microprocessor comprises a bus switch, a register/buffer operatively coupled to the bus switch, enable/disable pins operatively coupled to the bus switch and the register/buffer, and a system controller for detecting a type of the memory module and enabling one of the bus switch and register/buffer based on the type of the memory module detected. Further, the enable/disable pins are configured so that only one of the bus switch and the register/buffer is active at a time.
The bus switch and the register/buffer may be implemented in a single integrated circuit package and the system controller interfaces with the single integrated circuit package. The bus switch may be a transistor configured as a pass gate.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.
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Hwang David S.
Pelissier Gerald R.
King Justin
Rosenthal & Osha L.L.P.
Sun Microsystems Inc.
Thai Xuan M.
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