Dual mode MNOS memory with paired columns and differential sense

Details Dual mode MNOS memory with paired columns and differential sense Dual mode MNOS memory with paired columns and differential sense

1976-06-28

1978-05-16

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

G11C 1140

Patent

active

040902579

ABSTRACT:
A memory system utilizing an array of dual gate variable threshold MNOS memory transistors is disclosed which may be operated such that a single MNOS transistor is used to store each bit of digital information or in a second mode which utilizes two MNOS transistors for each bit stored. The threshold of the transistor interrogated is used to determine the state of a flip-flop comprising a pair of cross-coupled MNOS transistors. A particular transistor of the array is interrogated by coupling appropriate "row select" and "column select" signals to the row and column select terminals. Transistors comprising the first and second columns have their source terminals connected in common and to the drain terminal of the first transistor of the cross-coupled pair. Similarly for, the third and fourth columns. First and second reference transistors also have their source terminals respectively coupled to the drain terminals of the first and second transistors comprising said cross-coupled pair. In either mode, the cross-coupled pair is utilized as the sensing circuit for determining the threshold state of the MNOS memory transistor interrogated. The circuitry coupled to the drains of each transistor comprising the cross-coupled pair is identical resulting in a symmetrical circuit.

REFERENCES:
patent: 3728695 (1973-04-01), Bentchkowsky
patent: 3851317 (1974-11-01), Kenyon
Krick, Self-Differential Sensing of MNOS Memory Arrays, IBM Technical Disclosure Bulletin, vol. 16, No. 12, 5/74, pp. 4098-4099.

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