Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-04-12
2001-04-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S087000, C326S081000, C326S083000, C326S086000, C326S021000, C326S030000, C326S062000, C326S063000
Reexamination Certificate
active
06218863
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuitry; more particularly, to interface circuits useful for transmitting input/output (I/O) signals between an integrated circuit (IC) and external chips or systems.
BACKGROUND OF THE INVENTION
There are many different types of output circuits and logic devices employed in semiconductor integrated circuits for driving transmission lines that carry communications between the circuits. In the past, emitter coupled logic (ECL), transistor-transistor logic (TTL) and complimentary metal oxide semiconductor (CMOS) logic levels were widely used for interchip input/output interfacing. As the transmission of high-speed data became more prevalent, designers developed output circuits that provided very small amplitude signals, thereby making it possible to transfer data at high speeds while overcoming problems with distortion, ringing, and the like.
For example, the Gunning Transceiver Logic (GTL) output circuit described in U.S. Pat. No. 5,023,488 drives transmission lines with a signal having a logical amplitude in the range from about 0.8 volts to 1.4 volts. Today, many information processing devices such as computers and workstations, which transfer information at high data rates across shared bus circuits, employ GTL output circuits for interconnection to the bus transmission lines. Despite its wide use, however, GTL circuitry does have drawbacks.
One of the problems associated with GTL circuits is the occurrence of “ringing” on the transmission lines. This problem, along with proposed solutions, is described in U.S. Pat. No. 5,563,542; and U.S. Pat. No. 5,483,188. The latter patent describes an improved phase-output driver in which the output transistors are connected to a delay element. By precisely ordering which transistors are turned on and off, and the time delay therebetween, the edge rate for the output signal is controlled to reduce ringing and other noise affects.
U.S. Pat. No. 5,606,275 teaches the use of an analog-to-digital (A/D) converter for adjusting the impedance of the output driver circuitry to match the characteristic impedance of the load, thus preventing ringing. The technique of varying impedance to match the characteristic impedance of a digital communication transmission line is also described in U.S. Pat. No. 5,811,984.
Another drawback of GTL circuitry is that it continuously requires direct current. The problem of high power dissipation in data output buffer circuitry is discussed generally in U.S. Pat. Nos. 5,703,811 and 5,819,099. More specifically, U.S. Pat. No. 5,801,554 teaches an improved GTL compatible circuit which attempts to overcome the problem of power consumption.
The problem of power consumption is even more critical for mobile applications such as notebook or mini-notebook computing devices. There remains a need for an I/O interface circuit that is compatible with GTL levels used in standard information processors such as desktop computers and workstations while overcoming the aforementioned problems associated with GTL circuits for mobile computer applications.
SUMMARY OF THE INVENTION
A dual mode I/O interface circuit is described that is compatible with either GTL logic signals or traditional CMOS logic signals. In one embodiment, the I/O circuit comprises a differential sense amplifier having one input coupled to a connection node, and the other input coupled to a reference voltage. A pull-up circuit includes at least one P-type field-effect transistor coupled between a positive supply potential and the connection node. Also included is a pull-down circuit that includes at least one N-type field-effect transistor coupled between the connection node and a negative supply potential or ground.
The interface circuit further comprises logic circuitry coupled to the gate of the at least one P-type field-effect transistor of the pull-up circuit, and the gate of the at least one N-type field-effect transistor of the pull-down circuit. The logic circuitry controls the conductivity of the field-effect transistors responsive to an input signal and also a mode signal, such that a first representation of the input signal compatible with GTL logic signals as provided at the connection node when the mode signal is asserted. A second representation of the input signal compatible with CMOS logic levels is provided at the connection node when the mode signal is deasserted.
REFERENCES:
patent: 5023488 (1991-06-01), Gunning
patent: 5483188 (1996-01-01), Frodsham
patent: 5557221 (1996-09-01), Taguchi et al.
patent: 5563542 (1996-10-01), Watarai
patent: 5594367 (1997-01-01), Trimberger et al.
patent: 5606275 (1997-02-01), Farhang et al.
patent: 5703811 (1997-12-01), Yoo et al.
patent: 5801554 (1998-09-01), Momma et al.
patent: 5811984 (1998-09-01), Long et al.
patent: 5819099 (1998-10-01), Ovens
patent: 6034555 (2000-03-01), Taguchi et al.
patent: 6037803 (2000-03-01), Klein
patent: 6049221 (2000-04-01), Ishibashi
patent: 6075379 (2000-06-01), Haider et al.
Hsu Pochang
Nagaraj Ravi
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Tan Vibol
Tokar Michael
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