Dual mode clock alignment and distribution device

Details Dual mode clock alignment and distribution device Dual mode clock alignment and distribution device

2000-10-06

2004-02-03

Vo, Don N. (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

06687322

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to clock alignment devices, and more particularly to clock alignment devices that can operate in dual modes.
2. Description of the Related Art
Clocking devices play an integral part in most modern electronic systems. In synchronous systems, in particular, clocking devices are used to step desired system operations through various stages of signal processing. For example, modem computer systems typically employ clock devices to synchronize transfer and processing of data and control signals between various parts of the computer systems.
Computer systems generally include one or more central processing units (CPUs), a main memory, input/output (I/O) devices, mass storage devices (e.g., hard disks, optical disk drives, etc.), and one or more buses. The buses function to facilitate communication of data and control signals among the various components of a computer system. Some popular buses used in modem computer systems are peripheral component interface (PCI) bus, IDE bus, SCSI bus, etc.
The PCI bus, for example, is widely used to connect an increasing number of component devices in accordance with conventional PCI specification version 2.2. To facilitate communication, PCI adapters are typically implemented in such computer systems to properly synchronize communication and processing of the data and control signals between a bus and a computer component device.
FIG. 1
shows a PCI adapter
100
for interfacing a computer component device or digital device with a PCI bus. The PCI adapter
100
receives data signals (e.g., data, address, etc.) and a clock signal, which runs at the maximum clock speed of 66 Mhz. This translates to a clock period of 15 nanosecond (ns). The PCI adapter
100
processes the data signals and generates output signals. In this arrangement, however, the output signals are generated and output after a propagation delay typically ranging between 2 to 6 ns.
FIG. 2A
illustrates a more detailed schematic diagram of the PCI adapter
100
. The PCI adapter
100
includes core logic
202
, a flip-flop
208
, and a pair of delay elements
204
and
206
. The delay elements
204
and
206
receive input reference clock PCLKin from a PCI bus (not shown) and outputs delayed clocks PCLKCore and PCLKO, respectively. The PCLKCore clock is then provided to the core logic
202
to synchronize the operation of the core logic
202
. Similarly, the PCLKO clock is provided as a control clock to the flip-flop
208
. The core logic
202
interfaces data received from the PCI bus and outputs the data to the flip-flop
208
in response to the PCLKCore clock. The flip-flop
208
then outputs the data in response to the PCLKO clock.
In operation, however, the use of delay elements
204
and
206
typically generates a clock skew. For example,
FIG. 2B
shows a timing diagram of clocks PCLKCore and PCLKO of the PCI adapter
100
for PCLKin clock of 66 Mhz. The reference clock PCLKin is characterized by a period T of 15 ns. The delay element
204
delays the PCLKin clock and outputs PCLKCore with 5 ns delay D
1
to the core logic
202
. This delay allows the input data signal to settle for transmission to the core logic
202
. On the other hand, the delay element
206
is typically configured to provide substantially less delay than the delay element
204
. For example, the delay element
206
delays the PCLKin clock and outputs PCLKO with 2 ns delay D
2
to the output flip-flop.
While the delays D
1
and D
2
are suitable for conventional PCI specification version 2.2, these delays generally are not adequate for clock speed higher than 66 Mhz. For example, a latest enhancement to the conventional PCI protocol, specified as an addendum to PCI local bus specification version 2.2 and commonly known as PCI-X specification, which is incorporated herein by reference, allows clock speed of up to 133 Mhz. At 133 Mhz clock speed, the PCI adapter
100
would not provide sufficient clock margins to allow proper operation. Specifically, as the reference clock speed increases up to 133 Mhz with a period of 7.5 ns, the delays D
1
and D
2
of 5 ns and 2 ns become more significant. However, the PCI-X specification requires data output delay between ½ ns and 4 ns relative to the input clock PCLKin. With such large delays with respect to the reference clock, PCLKCore and PCLKO clock signals may not align properly with sufficient margins to allow the host adapter to generate proper output signals for PCI-X devices.
Thus, there is a need for clocking devices that can ensure proper operation of PCI devices in both conventional PCI mode and the newer PCI-X mode. In addition, what is also needed is clocking alignment and distribution devices that can accommodate different clock speeds with minimum clock skews.
SUMMARY OF THE INVENTION
The present invention fills these needs by providing dual mode clock alignment and distribution devices. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one aspect of the invention, the present invention provides a dual mode clock alignment device including a clock buffer cell, a phase-lock loop (PLL), and a first set and second set of buffers. The clock buffer cell is arranged to receive a first clock and delays the first clock. The PLL is arranged to receive the delayed first clock from the clock buffer and outputs a second clock. The first and second sets of buffers are arranged to receive the delayed first clock from the clock buffer cell for operating in a first clock mode. The first and second sets of buffers are further arranged to receive the second clock from the PLL for operating in a second clock mode. In this arrangement, the first set of buffers delays the received clock by a first delay to output a third clock and the second set of buffers delays the delayed clock by a second delay to output a fourth clock. When operating in the second clock mode, the first, third, and fourth clocks are all aligned.
In another aspect of the invention, the present invention provides a dual mode PCI adapter device for interfacing between a PCI bus and a PCI device. The PCI adapter device includes a clock buffer cell, a PLL, a first and second set of buffers, a core logic, and an output flip-flop. The clock buffer cell is arranged to receive and delay a first clock. The PLL arranged to receive the delayed first clock from the clock buffer, the PLL being configured to output a second clock. The first and second sets of buffers are arranged to receive the delayed first clock from the clock buffer cell for operating in a PCI mode. In addition, the first and second sets of buffers are further arranged to receive the second clock from the PLL for operating in a PCI-X mode. The first set of buffers delays the received clock by a first delay to output a third clock and the second set of buffers delays the received clock by a second delay to output a fourth clock. When operating in the PCI-X mode, the first, third, and fourth clocks are all aligned. The core logic includes a set of flip-flops and is arranged to receive and output data and address from the PCI bus in response to the third clock. The output flip-flop is coupled to receive the data from the logic circuit to output the data to the PCI device in response to the fourth clock.
In yet another aspect of the invention, a dual mode clock alignment and distribution device is disclosed. The dual mode clock alignment and distribution device includes a clock buffer cell, a PLL, a first and second set of buffers, a logic circuit, and a set of I/O cells. The clock buffer cell is adapted to receive and delay a first clock. The PLL is arranged to receive the delayed first clock from the clock buffer and output a second clock. The first set and a second set of buffers are arranged to receive the delayed first clock from the clock

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