Dual metal gate transistors for CMOS process

Details Dual metal gate transistors for CMOS process Dual metal gate transistors for CMOS process

2002-09-10

2004-09-21

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S655000, C438S657000, C438S663000, C438S667000

Reexamination Certificate

active

06794281

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to the field of semiconductor fabrication and more particularly to a fabrication process incorporating differing gate metals for n-channel and p-channel devices.
RELATED ART
In the field of semiconductor fabrication, it is typically desirable to fabricate n-channel and p-channel transistors with matching threshold voltages. In addition, it is desirable if the absolute value of the n-channel and p-channel threshold voltages are close to zero to increase the device speed. In conventional semiconductor processing, n-channel and p-channel threshold voltages are conventionally adjusted by a combination of channel implants and selective doping of a polysilicon gate. Typically, the use of channel implants is effective in adjusting the threshold voltages for n-channel devices but less effective for p-channel devices. In addition, the use of polysilicon gate structures is becoming unfeasible as gate dielectric thicknesses steadily decrease. More specifically, boron diffusion from p-type polysilicon gates into the transistor channel and poly depletion effects associated with devices having low thermal budget and thin gate oxides are making it increasingly difficult to incorporate polysilicon gates into advanced technologies. In addition, as semiconductor processing moves away from the use of silicon dioxide as a gate dielectric, chemical reactions between polysilicon and alternative gate dielectric structures render polysilicon less desirable as a gate of choice. Therefore, it would be highly desirable to implement a fabrication process in which n-channel and p-channel threshold voltages are matched and satisfactorily low. In addition, it would be desirable if the implemented process were compatible with alternative gate dielectric materials.


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