Dual metal gate transistors for CMOS process

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S369000, C257S368000, C257S366000, C257S365000

Reexamination Certificate

active

06545324

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to the field of semiconductor fabrication and more particularly to a fabrication process incorporating differing gate metals for n-channel and p-channel devices.
RELATED ART
In the field of semiconductor fabrication, it is typically desirable to fabricate n-channel and p-channel transistors with matching threshold voltages. In addition, it is desirable if the absolute value of the n-channel and p-channel threshold voltages are close to zero to increase the device speed. In conventional semiconductor processing, n-channel and p-channel threshold voltages are conventionally adjusted by a combination of channel implants and selective doping of a polysilicon gate. Typically, the use of channel implants is effective in adjusting the threshold voltages for n-channel devices but less effective for p-channel devices. In addition, the use of polysilicon gate structures is becoming unfeasible as gate dielectric thicknesses steadily decrease. More specifically, boron diffusion from p-type polysilicon gates into the transistor channel and poly depletion effects associated with devices having low thermal budget and thin gate oxides are making it increasingly difficult to incorporate polysilicon gates into advanced technologies. In addition, as semiconductor processing moves away from the use of silicon dioxide as a gate dielectric, chemical reactions between polysilicon and alternative gate dielectric structures render polysilicon less desirable as a gate of choice. Therefore, it would be highly desirable to implement a fabrication process in which n-channel and p-channel threshold voltages are matched and satisfactorily low. In addition, it would be desirable if the implemented process were compatible with alternative gate dielectric materials.


REFERENCES:
patent: 6066533 (2000-05-01), Yu
patent: 6130123 (2000-10-01), Liang et al.
patent: 6207589 (2001-03-01), Ma et al.
patent: 6261887 (2001-07-01), Rodder
patent: 6383879 (2002-05-01), Kizilyalli et al.
patent: 0899784 (1999-03-01), None
patent: 60045053 (1985-03-01), None
patent: 2000031291 (2000-01-01), None
patent: 2001196468 (2001-07-01), None
Lu et al, “Dual-Metal Gate Technology for Deep Submicron CMOS Transistors,” IEEE, Symposium on VLSI Technology Digest of Technical Paper, pp. 72-73 (2000).
Maiti et al., “Metal Gates for Advanced CMOS Technology,” SPIE Conference on Microelectronic Device Technology III, SPIE vol. 3881, pp. 46-57 (1999).
Clafin et al., “High-K Dielectrics and Dual Metal Gates: Integration Issues for New CMOS Materials,” Materials Research Society Symposium Proc. vol. 567, pp. 603-608 (1999).
Azuma et al., “Integration Technorology of Polymetal (W/WSiN/Poly-Si) Dual Gate CMOS for 1 Gbit DRAMs and Beyond,” IEEE, pp. 389-392 (1998).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Dual metal gate transistors for CMOS process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual metal gate transistors for CMOS process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual metal gate transistors for CMOS process will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3033374

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.