Dual memory channel interleaving for graphics and video

Details Dual memory channel interleaving for graphics and video Dual memory channel interleaving for graphics and video

2006-02-14

2006-02-14

Tung, Kee M. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Addressing

C345S540000

Reexamination Certificate

active

06999091

ABSTRACT:
Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.

REFERENCES:
patent: 5900865 (1999-05-01), Howe
patent: 6064407 (2000-05-01), Rogers
patent: 6301299 (2001-10-01), Sita et al.
patent: 6674443 (2004-01-01), Chowdhuri et al.
patent: 6690377 (2004-02-01), Tuomi

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