Dual-mask etch of dual-poly gate in CMOS processing

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S717000, C438S719000, C438S720000, C438S725000

Reexamination Certificate

active

06534414

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to complementary metal-oxide semiconductor (CMOS) manufacturing, and, more particularly, to a dual-polysilicon (dual-poly) gate fabrication method.
2. Description of the Related Art
Dual-poly gate technology is preferred to produce surface channel devices having small critical dimension (CD), e.g. CDs below approximately 0.25 micrometer (&mgr;m). Such surface channel devices have both N-type and P-type material formed separately by masked implants to a common thin film of polysilicon deposited on a substrate. During gate formation by etching, using a single mask for both the N and P features, the N and P materials respond to etching chemistries differently, i.e. the result is differential etching of the materials. This leads to undesirably and often unacceptably different feature profiles and oxide remnant between the P and N regions of the gate.
SUMMARY OF THE INVENTION
The invented method involves separately etching the P and N gate features in a dual-poly gate using dual masks, thereby permitting the etching chemistries to be tuned to the differentially responsive P and N materials that form the gate. The method involves a) providing a polysilicon layer of a first type over a first region of a semiconductor substrate; b) providing a polysilicon layer of a second type over a second region of the semiconductor substrate; c) depositing a metallic layer overlying the polysilicon layers in the first and second regions; d) depositing an anti-reflective layer overlying the metallic layer in the first and second regions; e) selectively etching the dielectric hard-mask multi-layer film to form a patterned outer hard-mask multi-layer; f) forming a first photoresist pattern overlying the patterned outer hard-mask multi-layer in the first region; g) first etching the metallic layer and the polysilicon layer of the second type to form a stacked gate structure in the second region; h) forming a second photoresist pattern overlying the patterned outer hard-mask multi-layer in the second region; and i) second etching the metallic layer and the polysilicon layer of the first type to form a stacked gate structure in the first region. Preferably, the first photoresist pattern and the second photoresist pattern define a nominal boundary therebetween, with the patterns having a predefined gap therebetween in a region around the boundary. Alternatively, the dual-mask technique is used on a non-hardmask dual-poly film stack and the top dielectric multi-layer film is replaced by an ARC film.


REFERENCES:
patent: 5355010 (1994-10-01), Fujii et al.
patent: 5863819 (1999-01-01), Gonzalez
patent: 5877535 (1999-03-01), Matsumoto
patent: 5918133 (1999-06-01), Gardner et al.
patent: 5945724 (1999-08-01), Parekh et al.
patent: 5985725 (1999-11-01), Chou
patent: 5989962 (1999-11-01), Holloway et al.
patent: 6010925 (2000-01-01), Hsieh
patent: 6010961 (2000-01-01), Hu
patent: 6017784 (2000-01-01), Ohta et al.
patent: 6107173 (2000-08-01), Han
patent: 6153534 (2000-11-01), Long et al.
patent: 6221708 (2001-04-01), Gonzalez et al.

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