Dual loop sensing scheme for resistive memory elements

Details Dual loop sensing scheme for resistive memory elements Dual loop sensing scheme for resistive memory elements

2005-07-05

2005-07-05

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S158000

Reexamination Certificate

active

06914838

ABSTRACT:
A method and apparatus for sensing a resistive state of a resistive memory element includes producing a first current related to a resistance of a memory cell. The first current is added to a second current during a first sensing time and subtracted from a third current during a second sensing time. The first, second and third currents are integrated over time using a capacitor, and a resulting voltage signal on the capacitor is timed using a clocked counter. A time average value of a digital output of the clocked counter is then related to the resistance of the memory cell, and hence to the resistive state of the resistive memory element.

REFERENCES:
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patent: 6317375 (2001-11-01), Perner
patent: 6504750 (2003-01-01), Baker
patent: 6577525 (2003-06-01), Baker
patent: 6693826 (2004-02-01), Black et al.

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