Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2002-08-19
2004-12-07
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S158000
Reexamination Certificate
active
06829188
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the reading of resistor-based memory devices such as magneto-resistive random access memory (MRAM) devices which store logic values as resistive states in a memory cell.
2. Description of the Related Art
FIG. 1
shows one example of a resistor based memory array architecture called a crosspoint array. The memory array
8
includes a plurality of row lines
6
arranged orthogonally to a plurality of column lines
12
. Each row line is coupled to each of the column lines by a respective resistive memory cell
14
. The resistance value of each memory cell stores one of two or more logical values depending on which of a plurality of resistance values it is programmed to exhibit. A characteristic of the crosspoint array having resistance cells
14
connected to row and column lines is that there are no memory cell access transistors in the array.
An MRAM device is one approach to implementing a resistance based memory. In an MRAM, each resistive memory cell typically includes a pinned magnetic layer, a sensed magnetic layer and a tunnel barrier layer between the pinned and sensed layers. The pinned layer has a fixed magnetic alignment, and a magnetic alignment of the sensed layer can be programmed to different orientations. The resistance of the cell varies, depending on the alignment of the sensed layer. One resistance value, e.g., a higher value, is used to signify a logic “one” while another resistance value, e.g., a lower value, is used to signify a logic “zero”. The stored data is read by sensing respective resistance values of the cells, and interpreting the resistance values thus sensed as logic states of the stored data.
For binary logic state sensing, the absolute magnitude of memory cell resistance need not be known; only whether the resistance is above or below a threshold value that is intermediate to the logic one and logic zero resistance values. Nonetheless sensing the logic state of an MRAM memory element is difficult because the technology of the MRAM device imposes multiple constraints.
An MRAM cell resistance is sensed at the column line of the addressed cell. In order to sense the cell, a row line connected to that cell is typically grounded while the remaining row lines and column lines are held at a particular voltage. Reducing or eliminating transistors from a memory cell tends to reduce cell real estate requirements, increasing storage density and reducing costs. A cell of a crosspoint array, as discussed above, includes no transistors. This is achieved by allowing each resistive element to remain electrically coupled to respective row and column lines at all times. As a result, when a memory cell is sensed it is also shunted by a significant sneak current path through the other memory cells of the addressed row line.
In a conventional MRAM device, the differential resistance between a logic one and a logic zero is typically about 50 K&OHgr;, or 5% of scale. Accordingly, a sensing voltage across a sensed MRAM device varies by about 5% of scale between the logic one and logic zero states.
One approach to sensing MRAM resistance is to integrate a current corresponding to the sensing voltage over time, and to sample the resulting integrated voltage after a given time period. This can be done by applying a voltage to an input of a transconductance amplifier, and accumulating a current output by the amplifier with a capacitor.
FIG. 2
illustrates the theoretical change of voltage on such a capacitor with time. The time interval t
m
that the capacitor voltage takes to climb from an initial voltage V
init
to a reference voltage V
ref
is related to the voltage applied at the input of the transconductance amplifier.
As shown in
FIG. 3
, however, this sensing scheme is vulnerable to stochastic noise. A noise component on the integrated voltage can readily overcome the signal being measured. The resulting measurement produces an erroneous result when the noisy voltage signal crosses the reference voltage (V
ref
) threshold at time t
err
.
Accordingly, a robust and reliable sensing method is needed for sensing the state of a resistive memory element.
BRIEF SUMMARY OF THE INVENTION
According to one aspect of the present invention, MRAM cell logic state is sensed by configuring an memory cell so as to form a sensing voltage across the cell that is related to a resistance of the cell. The sensing voltage is applied to an input of a transconductance amplifier, which outputs a sensing current related to the sensing voltage. The sensing current is integrated over time with an additional current and filtered through a digital counter to improve sensing circuit sensitivity.
During sensing, the sensing circuit progresses through several states. In a first state the sensing current is summed with a first positive current to form a first summed current that charges a capacitor. In a second state, the sensing current is summed with a second negative current, to form a second summed current that discharges the capacitor. The resulting voltage signal on the capacitor is compared to a reference voltage. A result of the comparison is used to control a clocked digital counter. An output count of the digital counter depends, on a time-averaged basis, on the sensing voltage. By comparing the count value of the digital counter to a digital threshold value at a known time interval after the counter is preset to a preset value, the logical state of the sensed MRAM cell can be ascertained.
These and other features and advantages of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.
REFERENCES:
patent: 6188615 (2001-02-01), Perner et al.
patent: 6504750 (2003-01-01), Baker
patent: 6577525 (2003-06-01), Baker
patent: 6693826 (2004-02-01), Black et al.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Phung Anh
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