Dual level wordline clamp for reduced memory cell current

Details Dual level wordline clamp for reduced memory cell current Dual level wordline clamp for reduced memory cell current

1998-06-15

1999-08-10

Nelms, David

Static information storage and retrieval

Read/write circuit

Including signal clamping

36518909, 36518911, G11C 1604

Patent

active

059368942

ABSTRACT:
The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.

REFERENCES:
patent: 4074237 (1978-02-01), Spampinato
patent: 4156941 (1979-05-01), Homma et al.
patent: 4546457 (1985-10-01), Nozaki et al.
patent: 5287307 (1994-02-01), Fukuda et al.
patent: 5333122 (1994-07-01), Ninomiya
patent: 5796651 (1998-08-01), Horne et al.

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