Dual-level stacked flash memory cell with a MOSFET storage...

Details Dual-level stacked flash memory cell with a MOSFET storage... Dual-level stacked flash memory cell with a MOSFET storage...

2005-06-16

2008-03-04

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257SE21103, C257SE21304, C438S257000, C438S593000, C438S258000, C438S259000

Reexamination Certificate

active

07339226

ABSTRACT:
The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erased and read by alternate modes of operation wherein active regions operate as source and drain, and then drain and source. The upper bit is programmed and erased independent of the lower bits. However, reading of the upper bit depends upon read values of the lower bits. Additional levels are employed to store more than 3 bits of information.

REFERENCES:
patent: 5894146 (1999-04-01), Pio et al.
patent: 5923975 (1999-07-01), Rolandi
patent: 6329254 (2001-12-01), Cremonesi et al.
patent: 6493265 (2002-12-01), Satoh et al.
patent: 6815764 (2004-11-01), Bae et al.
patent: 6818512 (2004-11-01), Hsieh
patent: 2002/0163031 (2002-11-01), Liu et al.
patent: 2003/0007384 (2003-01-01), Shimizu
patent: 2003/0039146 (2003-02-01), Choi

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