Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-06
2001-10-02
Fahmy, Wael (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C438S239000, C438S395000, C438S592000, C438S657000, C438S652000
Reexamination Certificate
active
06297528
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of preventing auto-doping from the top polysilicon layer of a capacitor in the manufacture of integrated circuits.
(2) Description of the Prior Art
In the manufacture of integrated circuit devices, a so-called mixed-mode product fabrication is one in which MOSFET device structures and capacitor structures are formed on the same wafer. A capacitor is formed by using two polysilicon layers as the top and bottom plates of the capacitor with a dielectric layer therebetween. The polysilicon layers are formed either by in-situ polysilicon deposition or POCl-doped polysilicon. In either case, the dopant; that is, phosphorus; is spread throughout the polysilicon layer and tends to diffuse out of the polysilicon in post-poly etch thermal cycles. The out-diffused dopants will reach the silicon surface if the oxide on the surface is not thick enough to prevent further diffusion into the substrate in subsequent thermal processes. In a PMOS device on the same wafer, the out-diffused phosphorus will laterally and vertically increase the n-type dopant concentration near or under the edge of the channel region after thermal cycles. This is called auto-doping.
FIG. 1
illustrates this auto-doping phenomenon. A capacitor
50
has been fabricated overlying a field oxide region
12
on a semiconductor substrate
10
. The capacitor comprises a polysilicon bottom electrode
41
, dielectric layer
43
, and top polysilicon electrode
45
. Elsewhere on the wafer, a PMOS gate electrode device
52
has been formed. During thermal cycles, dopant
55
from the top capacitor electrode
45
out-diffuses into the atmosphere and into the substrate at the edge of the PMOS channel region
57
. Because of the n-type dopant near the channel region, higher gate voltage will have to be applied to invert the channel region in order to form a conducting channel from source to drain. This results in a threshold voltage (V
t
) shift. In auto-doping, the n-type dopants come from the same wafer on which the PMOS devices are fabricated, as illustrated in
FIG. 1
, or dopants may come from the wafers positioned either before or after the wafer on which the PMOS devices are fabricated.
It is desired to prevent auto-doping. Two approaches to preventing auto-doping can be adopted. In one approach, the thickness of the oxide on the surface of the substrate can be increased so that it can retard the penetration of dopants. This approach is taught in the prior art of U.S. Pat. No. 5,461,002 to Safir and in U.S. Pat. Nos. 5,492,868 to Lin et al and 4,925,809 to Yoshiharu et al.
A second approach to preventing auto-doping is to prevent the out-diffusion of dopants from the n-type capacitor plate. This approach is taught in U.S. Pat. Nos. 5,070,382 to Cambou and 4,894,349 to Saito et al.
A third approach does not prevent auto-doping, but etches away those areas that have been auto-doped. This approach is taught in U.S. Pat. No. 5,461,002 to Safir.
The process of the present invention takes the second approach of preventing out-diffusion of dopants from the capacitor plate.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a capacitor and PMOS devices in a mixed-mode product production.
Another object of the invention is to provide a method of fabricating a capacitor in which out-diffusion of dopant from the top capacitor plate is prevented.
Another object is to provide a method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which there is no auto-doping of the PMOS channel region.
A further object of the present invention is to provide a composite polysilicon top plate electrode in the fabrication of a capacitor which prevents out-diffusion of dopant from the capacitor plate.
A still further object is to provide a method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region.
In accordance with the objects of this invention a new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is achieved. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilicon layer comprises a lower doped polysilicon layer and an upper undoped polysilicon layer. The composite polysilicon layer and capacitor dielectric layer are etched away where they are not covered by a mask to leave the capacitor dielectric layer and the composite polysilicon layer overlying the bottom plate electrode wherein the composite polysilicon layer forms the top plate electrode of the capacitor to complete the formation of an integrated circuit having a capacitor and PMOS devices fabricated on the same wafer. The upper undoped polysilicon layer prevents out-diffusion from the lower doped polysilicon layer during thermal cycles thus preventing auto-doping.
Also in accordance with the objects of this invention, a mixed-mode integrated circuit device having a composite polysilicon top plate capacitor electrode which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is achieved. A PMOS gate electrode overlies a semiconductor substrate in a first region of the integrated circuit device. Source and drain regions lie within the semiconductor substrate adjacent to the PMOS gate electrode. A capacitor overlies the semiconductor substrate in a second region of the integrated circuit device. The capacitor comprises: a bottom plate electrode overlying the semiconductor substrate, a capacitor dielectric layer overlying the bottom plate electrode, and a top plate electrode comprising a composite polysilicon layer overlying the capacitor dielectric layer. The composite polysilicon layer comprises a lower doped polysilicon layer and an upper undoped polysilicon layer. The upper undoped polysilicon layer prevents out-diffusion from the lower doped polysilicon layer during thermal cycles thus preventing auto-doping.
REFERENCES:
patent: 4894349 (1990-01-01), Saito et al.
patent: 4925809 (1990-05-01), Yoshiharu et al.
patent: 4997775 (1991-03-01), Cook et al.
patent: 5070382 (1991-12-01), Cambou
patent: 5461002 (1995-10-01), Safir
patent: 5492868 (1996-02-01), Lin et al.
patent: 5646061 (1997-07-01), Wang et al.
patent: 5837582 (1998-11-01), Su
patent: 5872045 (1999-02-01), Lou et al.
patent: 5913119 (1999-06-01), Lin et al.
Chen Chien-Feng
Chiou Shyh-Perng
Berezny Neal
Fahmy Wael
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