Dual layer patterning scheme to make dual damascene

Details Dual layer patterning scheme to make dual damascene Dual layer patterning scheme to make dual damascene

2006-07-18

2006-07-18

Norton, Nadine (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S736000, C216S047000

Reexamination Certificate

active

07078348

ABSTRACT:
One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.

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