Dual layer etch stop barrier

Details Dual layer etch stop barrier Dual layer etch stop barrier

2003-04-14

2004-01-20

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S712000, C438S637000, C438S724000

Reexamination Certificate

active

06680259

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to the manufacture of integrated circuit (I/C) chips and particularly to the fabrication or processing of a silicon substrate to form the circuitry for the I/C chip. During one stage of manufacture of I/C chips, a silicon dioxide layer is applied over a silicon substrate. The silicon dioxide must be etched at various places to provide openings to the substrate for electrical connections. One conventional technique of etching is by means of reactive ion etching (RIE). With reactive ion etching it is conventional to provide an etch stop barrier between the silicon substrate and the silicon dioxide layer formed thereon. One conventional etch stop barrier is silicon nitride (Si
x
N
y
). These silicon nitride barriers are conventionally deposited by low pressure chemical vapor deposition (LPCVD) utilizing conventional equipment. In one embodiment mixtures of silane (SiH
4
) and ammonia (NH
3
) are utilized as an ambient to provide the necessary silicon and nitrogen moieties for the formation of the silicon nitride.
However, it has been found in the past that there were variations from process to process of forming the Si
x
N
y
barrier in the effectiveness of the nitride barrier in its selectivity with respect to SiO
2
when reactive ion etching the SiO
2
. When etching SiO
2
it is desirable to have as much selectivity as possible of the etch stop with respect to the SiO
2
so as to allow a minimum thickness of the etch stop to be applied. It was also found that there were variations in the resulting barrier in the effectiveness of the silicon nitride to prevent passing of positive mobile ions (PMI) which may occur during subsequent processing due primarily to contaminants introduced into the SiO
2
layer. Positive mobile ion contamination (PMIC) such as in a gate oxide of CMOS devices must be reduced to a minimum. Thus a requirement of the silicon nitride barrier is that it act to effectively block positive mobile ions from penetrating into the substrate during subsequent processing steps.
Therefore it is desirable to provide a silicon nitride barrier that is both highly selective to etching of SiO
2
and also effective to block the passage of positive mobile ions in subsequent processing steps.
SUMMARY OF THE INVENTION
According to the present invention, a method for reactive ion etching of SiO
2
with an etch stop barrier for use in such an etching is provided. It has been found that a silicon nitride (Si
x
N
y
) barrier having a Si
x
to N
y
ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Si
x
to N
y
(x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO
2
but a poor barrier to positive mobile ion contamination. The technique of the present invention includes providing a substrate which conventionally is a doped silicon substrate, and forming a barrier of silicon nitride on the substrate which barrier has two sections or layers. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. Preferably the two sections are formed by forming one section, referred to as the lower section adjacent to silicon substrate with a silicon to nitrogen ratio of less than about 0.8 and preferably about 0.75 which is the stoichiometric ratio of silicon to nitrogen. The second section, or upper section is preferably formed with the ratio of the silicon to nitrogen of greater than about 0.8 and preferably at least about 1.0. Preferably the two sections together are from about 50 to about 100 nanometers thick and in the preferred embodiment, each section is about 25 to 50 nanometers thick.


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