Dual layer encapsulation coating for III-V semiconductor compoun

Details Dual layer encapsulation coating for III-V semiconductor compoun Dual layer encapsulation coating for III-V semiconductor compoun

1987-01-14

1987-12-22

Pianalto, Bernard D.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156643, 156653, 427 37, 427 38, 427259, 427264, 427265, 4273766, 437227, 437241, B44C 122

Patent

active

047145188

ABSTRACT:
A method for providing a dual layer diffusion mask or encapsulation coating for use with III-V compound semiconductors, the dual layer coating comprising an inner layer of silicon which closely matches the coefficient of thermal expansion of the III-V compound semiconductor and an outer layer of silicon nitride which is relatively impermeable to subsequent metallization and for thereafter applying metallized contacts to the III-V compound semiconductor through selectively etched openings in the diffusion mask or encapsulation coating.

REFERENCES:
patent: 3325392 (1967-06-01), Rummel
patent: 4181564 (1980-01-01), Fogarty et al.
patent: 4223048 (1980-09-01), Engle, Jr.
patent: 4333965 (1982-06-01), Chow et al.
patent: 4342617 (1982-08-01), Fu et al.
patent: 4395438 (1983-07-01), Chiang
patent: 4603059 (1986-07-01), Kiyosumi et al.

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