Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-12-18
2001-04-17
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S786000, C438S952000, C427S126300, C427S099300
Reexamination Certificate
active
06218292
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of manufacturing a semiconductor device employing an anti-reflective coating during photolithography. The invention is particularly applicable to the manufacture of semiconductor devices having sub 0.35 &mgr;m circuitry.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration require responsive changes in conductive patterns, which is considered one of the most demanding aspects of ultra large scale integration technology. High density demands for ultra large scale integration semiconductor wiring require increasingly denser arrays with minimal spacing between conductive lines. The increasing demands for high densification impose correspondingly high demands on photolithographic techniques.
During the manufacture of a semiconductor device, light from the stepper is passed through a mask and the pattern transferred to the underlying photoresist layer. However, when the substrate underlying the photoresist layer is highly reflective, e.g., metal and polysilicon layers, light reflections can destroy the pattern resolution by several mechanisms, including off-normal incident light reflected back from the photoresist that is intended to be masked, incident light reflected off device features exposing “notches” in the photoresist, and thin film interference effects leading to linewidth variations when photoresist thickness changes are caused by irregular wafer topography.
Photolithographic techniques conventionally employed during various phases in the manufacture of semiconductor devices comprise forming an anti-reflective coating (ARC), also characterized as an anti-reflective layer (ARL), typically a bottom ARC positioned between a substrate, e.g., a dielectric or conductive layer, and a photoresist layer. ARCs are conventionally made of various materials, including organic and inorganic materials. For example, inorganic materials conventionally employed for ARCs include silicon nitride, silicon oxynitride, &agr;-carbon, titanium nitride, silicon carbide and amorphous silicon. Organic materials conventionally employed for ARCs include spin-on polyimides and polysulfones. Conventional ARCs are designed by appropriate adjustment of variables such as composition, deposition conditions and reaction conditions, to exhibit the requisite optical parameters, e.g., index of refraction (n) and extinction coefficient (k), to suppress multiple interference effects caused by the interference of light rays propagating in the same direction due to multiple reflections in the photoresist layer. The effective use of an ARC enables patterning and alignment without disturbance caused by such multiple interference effects, thereby improving linewidth accuracy and alignment, critical factors with respect to achieving fine line conductive patterns with minimal interwiring spacing. The use of an ARC is particularly significant when forming a via or contact hole over a stepped area, as when etching a dielectric layer deposited on a gate electrode and gate oxide formed on a semiconductor substrate in manufacturing a field effect transistor. The physics involved in ARCs is known and the use of ARCs is conventional and, hence, will not be set forth herein detail. See, for example, T. Tanaka et al., “A New Photolithography Technique with Antireflective Coating on Resist: ARCOR,” J. Electrochem. Soc., Vol. 137, No. 12, December 1990, pp. 3900-3905.
ARCs have improved the accuracy of ultra-violet and deep ultra-violet lithography, and expanded the use of ion beam, I-line, KrF and ArF excimer laser lithography. T. Ogawa et al., “SiO
x
N
y
:H, high performance anti-reflective layer for current and future optical lithography.” Efforts have been made to engineer the optical parameters of an ARC, as by adjusting process variables impacting the refractive index during plasma enhanced chemical vapor deposition (PECVD). T. Gocho et al., “Chemical Vapor Deposition of Anti-Reflective Layer Film for Excimer Laser Lithography,” Japanese Journal of Applied Physics, Vol. 33, January 1994, Pt. 1, No. 1B, pp. 486-490.
In copending application U.S. Pat. No. 5,710,067 filed on Jun. 7, 1996, an anti-reflective film comprising silicon oxime having the formula Si
1−(x+y+z)
N
x
O
y
H
z
, wherein x, y and z represent the atomic percentage of nitrogen, oxygen and hydrogen, respectively, is disclosed for use as an ARC. The disclosed silicon oxime ARC typically comprises 15-20 at. % oxygen and about 10-20 at. % hydrogen, and is formed employing a stoichiometric excess of nitrogen sufficient to substantially prevent bonding between silicon atoms and oxygen atoms.
Conventional techniques for manufacturing a semiconductor employ various types of ARCs, including a bottom ARC formed beneath the photoresist layer to reduce substrate reflections, and a top ARC deposited over the photoresist layer to reduce second-auto reflections. Bottom ARCs have emerged as the most effective in reducing reflections while interfering the least with the photolithographic processes. A conventional application of a bottom dielectric ARC is schematically illustrated in
FIG. 1
, wherein dielectric bottom ARC
11
is formed on substrate
10
, which substrate
10
comprises either a dielectric layer or conductive layer. A photoresist layer
12
is formed on bottom ARC
11
and exposed through a patterned mask (not shown) to irradiation
13
. The reflected light, cancelled by a phase-shift cancellation at one-half wavelength, is shown by arrows
13
A and
13
B.
As design specifications are reduced below 0.35 &mgr;m, greater demands are placed upon the already strained requirements of photolithography. For example, as design features shrink below 0.35 &mgr;m, ARCs are required to suppress more than 99% of substrate-reflected light, meet stringent photoresist and device contamination requirements and operate at extended UV wavelengths. Such requirements cannot be met by conventional ARCs. For example, with features shrinking well below 0.35 &mgr;m and stepper productions systems shifting to shorter wavelengths, many conventional bottom ARCs result in reflective notching and no longer maintain acceptable linewidth variations. Conventional approaches resort to chemical vapor deposited dielectric ARCs and fine tuning optical parameters, such as the index of refraction (n) and extinction coefficient (k), as well as optimizing the thickness (d) of the ARC. See, for example, Benchor et al., “Dielectric Anti-Reflective Coatings for DUV Lithography,” Solid State Technology, March 1997, pp. 110-114. Notwithstanding such efforts, conventional photolithographic capabilities constitute a severe limiting factor in reducing the design rule or maximum dimension below 0.35 &mgr;m, particularly when forming a pattern on a substantially transparent dielectric substrate.
Conventional deep UV lithography utilizes bottom ARCs comprising both spin on films as well as various compounds of silicon, oxygen and/or nitrogen, e.g., silicon nitrides, silicon oxides and silicon oxynitrides. Such bottom anti-reflective coatings have been relatively successful in modifying or eliminating the amount of reflective energy from a substrate into a photoresist layer when the underlying substrate is optically infinite, i.e., when the substrate will only reflect incident energy, such as i-line or deep UV irradiation, from its top surface. However, a substrate or film that is not optically infinite will reflect and/or transmit energy at every interface within the substrate. Such reflections result in what is known as “reflective notching” which contributes to poor circuit design control.
Reflective notching is schematically illustrated in
FIG. 2
, wherein dielectric layer
20
, e.g., a layer of boron phosphorous tetraethoxy silicate (BPSG), is applied over structures
21
and
22
. Structure
21
comprises sequentially formed first polysilicon layer
21
A, dielectric layer
21
B, second polysilicon layer
21
C, metal silicide layer
21
D, such as tungsten silicide, a
Advanced Micro Devices , Inc.
Bowers Charles
Kielin Erik J
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