Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2002-09-26
2003-11-04
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S300000, C438S231000, C438S510000, C438S549000, C438S662000
Reexamination Certificate
active
06642122
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices with sub-micron dimensions. The present invention has particular applicability in manufacturing high density semiconductor devices with transistors having reduced short-channel effects.
BACKGROUND ART
The increasing demand for micro-miniaturization requires scaling down various horizontal and vertical dimensions in various device structures. As the thickness of the ion implanted source/drain junctions of transistors is scaled down, there is a corresponding scaled increase in the substrate channel doping in order to maintain a constant electric field in the transistor channel for higher speed performance. These objectives are achieved, in part, by not only forming shallow junctions but also forming source/drain extensions with an abrupt junction/dopant profile slope in proximity to the transistor channel in order to reduce penetration of the source/drain dopant into the transistor channel which occurs as the junction/profile slope becomes less abrupt. Such short channel effects result in poor threshold voltage roll-off characteristics for sub-micron devices.
There exists a continuing need for methodology enabling the fabrication of semiconductor devices containing transistors with source/drain extension junction/profiles which are shallow, abrupt and have a high surface concentration.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device having reduced short-channel effects.
Another advantage of the present invention is a method of manufacturing a semiconductor device having scaled MOSFETs with very abrupt and graded halo profiles for reduced short-channel effects.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method manufacturing a semiconductor device, the method comprising: forming a gate electrode over an upper surface of a substrate with a gate insulating layer therebetween; forming deep source/drain regions in the substrate on opposite sides of the gate electrode; ion implanting to form deep amorphized regions on each side of the gate electrode extending into the substrate to a first depth; ion implanting an impurity into the deep amorphized regions to form deep halo implants; laser thermal annealing to recrystallize the deep amorphized regions and to activate the deep halo implants to form deep halo regions; ion implanting to form shallow amorphized regions extending into the substrate to a second depth, less than the first depth, within the deep halo regions; ion implanting an impurity into the shallow amorphized regions to form shallow halo implants; and laser thermal annealing to recrystallize the shallow amorphized regions and to activate the shallow halo implants to form shallow halo regions.
Embodiments of the present invention comprise ion implanting to form third amorphized regions within the shallow halo regions, ion implanting an impurity into the substrate to form shallow source/drain implants within the third amorphized regions, and laser thermal annealing to activate the shallow source/drain implants to form shallow source/ drain extensions extending into the substrate to a third depth less than the second depth. Embodiments of the present invention further include forming an oxide liner on side surfaces of the gate electrode extending on a portion of the surface of the substrate on each side of the gate electrode, forming sidewall spacers, comprising silicon nitride, on the oxide liner, ion implanting to form the deep source/drain implants, annealing to form the deep source/drain regions, removing the sidewall spacers and oxide liner, and ion implanting to form the deep amorphized regions. Embodiments of the present invention further include forming the deep source/drain regions and shallow source/drain extensions with impurities of a first conductivity type and forming the deep and shallow halo regions with impurities of a second conductivity type, opposite the first conductivity type. Embodiments of the present invention also comprise forming the deep halo regions at a first impurity concentration and forming the shallow halo regions with a second impurity concentration greater than the first impurity concentration.
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Advanced Micro Devices , Inc.
Everhart Caridad
Luu Chuong A
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