Dual landing pad structure in an integrated circuit

Details Dual landing pad structure in an integrated circuit Dual landing pad structure in an integrated circuit

1996-12-03

1999-08-31

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257758, 257774, 257385, H01L 23485

Patent

active

059457384

ABSTRACT:
A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

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