Dual interrupt vector mapping

Details Dual interrupt vector mapping Dual interrupt vector mapping

1999-10-01

2002-12-31

Dharia, Rupal (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt prioritizing

C710S265000

Reexamination Certificate

active

06502152

ABSTRACT:

This application claims priority to S.N. 99400550.2, filed in Europe on Mar. 8, 1999 (TI-27764EU) and S.N. 98402455.4, filed in Europe on Oct. 6, 1998 (TI-28433EU).
FIELD OF THE INVENTION
The present invention relates to digital microprocessors, and more particularly to interrupt mechanisms for digital microprocessors.
BACKGROUND OF THE INVENTION
Microprocessors are general purpose processors which require high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. An interrupt response mechanism in a microprocessor typically includes an interrupt vector table for identifying the location of interrupt service routines.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in, but not exclusively, applications such as mobile telecommunications applications, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a microprocessor that is a programmable digital signal processor (DSP), offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The microprocessor is operable to respond to an interrupt request from a plurality of sources. The microprocessor has means for receiving a plurality of interrupt requests from the plurality of sources, means for retrieving a first interrupt vector from a first memory circuit in response to a first interrupt request from a first source selected from the plurality of sources. The microprocessor also has means for retrieving a second interrupt vector from a second memory circuit in response to a second interrupt request from a second source selected from the plurality of sources; wherein the second memory circuit is distinct from the first memory circuit. The microprocessor has means for executing a first interrupt service routine from a plurality of interrupt service routines in response to the first interrupt vector and a second interrupt service routine from the plurality of interrupt service routines in response to the second interrupt vector.
In accordance with another aspect of the present invention, there is a first memory circuit connected to the microprocessor operable to store a value for the first interrupt vector, a second memory circuit connected to the microprocessor operable to store a value for the second interrupt vector; and a host processor interface connected to the second memory circuit, wherein the host processor interface is operable to provide the second interrupt request.
In accordance with another aspect of the present invention, there is a host processor connected to the host processor interface, such that the host processor interface is operable to cause a different value to be stored in the second memory for the second interrupt vector in response to the host processor, and such that the host processor interface is operable to provide the second interrupt request in response to the host processor.
In accordance with another aspect of the present invention, a method of operating a digital system is provided. A microprocessor is operable to respond to an interrupt request from a plurality of sources by performing the following steps: receiving a plurality of interrupt requests from the plurality of sources; determining an interrupt number of a highest priority interrupt request of the plurality of interrupt requests; retrieving a first interrupt vector from a first memory circuit in response to a first interrupt request from a first source selected from the plurality of sources; executing a first interrupt service routine from a plurality of interrupt service routines in response to the first interrupt vector; retrieving a second interrupt vector from a second memory circuit in response to a second interrupt request from a second source selected from the plurality of sources; wherein the second memory circuit is distinct from the first memory circuit; and executing a second interrupt service routine from the plurality of interrupt service routines in response to the second interrupt vector.
In accordance with another aspect of the present invention, the address of the first interrupt vector in the first memory circuit is formed by combining a value stored in a first pointer register and the interrupt number if the value of the interrupt number is within a first range, the address of the second interrupt vector in the second memory circuit is formed by combining a value stored in a second pointer register and the interrupt number if the value of the interrupt number is within a second range.


REFERENCES:
patent: 5283880 (1994-02-01), Marcias-Garza
patent: 5394544 (1995-02-01), Motoyama et al.
patent: 5812760 (1998-09-01), Mendenhall et al.
patent: 0992902 (2000-12-01), None

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