Dual interposer packaging for high density interconnect

Details Dual interposer packaging for high density interconnect Dual interposer packaging for high density interconnect

2001-12-28

2004-11-02

Vigushin, John B. (Department: 2841)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S778000, C361S767000, C361S768000, C324S755090, C324S765010

Reexamination Certificate

active

06812485

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more specifically relates to testing and debugging semiconductor devices.
2. Discussion of the Related Art
A variety of packaging styles are known for semiconductor devices. Through-hole packages and surface mount packages such as peripheral leaded and area arrays are examples of several semiconductor package styles. These package styles, however, become problematic at higher operating frequencies.
More specifically, at high frequencies, even the relatively short leads of standard surface mount and through-hole mount integrated circuit (IC) packages tend to act like antennas, radiating electromagnetic fields outwardly therefrom. Even home computers today operate at clock speeds of 1 GHz or higher. Other specialized computing devices operate at even higher speeds. The high frequency signals input to and output from an IC pass across the chip leads. Longer package leads result in a more severe “antenna” effect, and thus, more intense electromagnetic interference (EMI).
As is known, EMI is disruptive to the proper operation of other circuit components proximately located to the source of the EMI. Accordingly, there is an identifiable need to reduce the levels of EMI generated. As is further known, this may be achieved by reducing the lead length of integrated circuit components. Area array packages, such as land grid array (LGA) packages, are a known package style that have a lessened radiation of EMI because of much shorter lead length.
LGA packages are devices without terminations on the bottom. The easiest way to envision an LGA device is to picture a semiconductor device with nothing but tiny round gold plated contact pads on the bottom. Typically, LGA packages connect to a printed circuit board (PCB) through a socket beneath the packages. The area array reduces package size and increases lead pitch, leading to higher assembly yields. More particularly, an LGA is a type of packaged integrated circuit in which one or more integrated circuit chips are mounted on a surface of a substrate, and electrical connection to electrically conductive material not part of the packaged integrated circuit, such as a PCB, is made by an intermediary device or socket with pins, springs, or something that can spring up and make contact with the contact pads located on a surface of the substrate opposite the surface to which the integrated circuit chip or chips are attached. The integrated circuit chip or chips are typically encapsulated by, for instance, plastic to protect the integrated chip or chips from the external environment. The integrated circuit chip is electrically connected to the substrate by wirebonding, tape-automated bonding, or flip-chip interconnection. LGAs allow a high density of external chip connections to be made as compared to other packaged integrated circuits having leads extending from the package periphery.
Flip chip interconnect technology supports “area array interconnect,” in which the chip is typically mechanically and electrically connected through an array of solder bumps on the active face of the chip. This technique increases the number of connections that can be made for a given chip size and can also improve electrical performance by reducing inductance and capacitance. The chip is attached to the substrate face down and is typically reinforced with an epoxy underfill.
From a manufacturing point of view, LGA packages have many virtues. An LGA-packaged device can pack the same processing power as a peripherally leaded quad flat pack (QFP)-packaged device in less volume, making LGA chips thinner and lighter. LGA also offer designers flexibility, allowing them to maximize the density of connections per chip to improve high-frequency operation.
Unfortunately, the dense array of contact pads makes testing the modules very difficult. The difficulty is increased where the module must be attached to another device, such as a PCB, for testing. For example, some modules must be attached to the system board before they can be completely tested. Testing these modules requires access to the contact pads be provided while the module is attached to the system board. Unfortunately, it is especially difficult, and in some cases impossible, to probe the input/output contact pads on the module when it is attached to the system board because the body of the module and the system board block access to the contact pads.
In the past, one way designers used to test and debug LGA modules was to form testing contact pads into the system board that provide contact points to the contact pads. Unfortunately this requires additional real estate on the system board, an unacceptable solution in many cases. Additionally, these types of landing pads generally require a specialized and expensive probing tool with a long lead-time required to build it.
Another method designers have used to debug and develop LGA packaged devices was to package them in a simplified package such as a pin grid array package (PGA), with the input/output connections through standard pinouts and then design and build a specialized test system board that is used only for debugging and testing. This specialized test system board would be similar to the normal system board, but with the design changes necessary to use the PGA modules instead of the LGA module. The designer could then use an interface card to connect to the specialized test system board to the overall system for testing.
The specialized test system board would be specially designed to provide landing pads for test probes that can be used to provide access to the contact pads and connect to a logic analyzer and/or other measurement devices. Thus, the designer was able to access the contact pads on the LGA module and test the module while it is connected to the overall system through the test PCB. Unfortunately, designing and building a specialized PGA package and a specialized test system board simply for the testing of the module was exceedingly time consuming and expensive. In particular, it requires the design and development of two packages, a test PGA package and an LGA module used for final packaging. Additionally, it requires special boards to be designed. The specialized test system board with its extra landing pads for testing and the normal system board without the landing pads that will be used in the final product.
Thus, what is needed is a method and apparatus to provide debugging and testing of LGA modules while on the system board or other packaging that does not require the specialized test packages or specialized test system boards, and this new LGA package does not require the use of valuable real estate on the system board for testing contact pads.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to a method and apparatus that allows additional contact pads to be added to a package to support debug and test operations. Preferably, the additional contact pads are added to the top surface of the LGA, so as not to utilize precious contact area on the bottom surface of the LGA. Furthermore, the top surface contact pads possess the same contact density, signal integrity, and reliability as the bottom surface contact pads, without degrading the bottom surface contacts pads' characteristics in any way.
In a preferred embodiment, a circuit board apparatus includes a semiconductor package and an interposer for receiving the semiconductor package. The semiconductor package preferably includes a substrate having a matrix of conductive contact pads on both the top and bottom surfaces of the substrate. The interposer preferably includes a body having a matrix of contact bumps that provide an electrical path from the LGA package to the PCB. Each interposer contact bump includes electrically conductive surfaces that are shaped to abut a contact pad of the LGA package and a contac

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