Dual insulating layer methods for forming integrated circuit gat

Details Dual insulating layer methods for forming integrated circuit gat Dual insulating layer methods for forming integrated circuit gat

1997-01-21

1999-08-10

Booth, Richard

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438738, 438740, H01L 21302

Patent

active

059358750

ABSTRACT:
A second insulating layer is used to mask a first insulating layer on a second gate electrode, during fabrication of a conductive contact adjacent a first gate electrode which is spaced apart from the second gate electrode. By using the second insulating layer as a sacrificial insulating layer during etching of the conductive contact, thinning of the first insulating layer on the second gate electrode may be prevented. In particular, first and second spaced apart gate electrodes are formed on an integrated circuit surface. The first and second spaced apart gate electrodes include first and second sidewalls, respectively. The first insulating layer and the second insulating layer are formed on the integrated circuit surface, including on the first and second gate electrodes. The second insulating layer is removed from the first gate. The first insulating layer is etched on the first gate to thereby form first spacers on the first sidewalls. A conductive contact is formed on the integrated circuit face, adjacent the first gate electrode and extending onto the first sidewall. The second insulating layer is removed from on the second gate and the first insulating layer is etched on the second gate, to thereby form second spacers on the second sidewalls.

REFERENCES:
patent: 4484978 (1984-11-01), Keyser
patent: 5786249 (1996-03-01), Dennison

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