Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-06-03
2000-11-07
Elms, Richard
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438622, 438228, 438175, 437228, H01L 214763
Patent
active
061436461
ABSTRACT:
A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions (30) only in critical areas where low-K dielectric material is absolutely needed. Other portions of the wafer remain covered with conventional oxide (24) so that adverse impacts of low-K dielectric material is minimized. Conductive material (38, 40, and 42) is then formed to complete dual inlaid contact structures whereby low-K dielectric plugs (30) reduce cross talk and capacitance within the final structure.
REFERENCES:
patent: 3944447 (1976-03-01), Magdo et al.
patent: 5204288 (1993-04-01), Marks et al.
patent: 5510645 (1996-04-01), Fitch et al.
patent: 5880018 (1999-03-01), Boeck et al.
R. V. Joshi, et al., "A Novel Application of Polyimide-W-Al/Cu for VLSI Interconnect", Jun. 11-12, 1991 VMIC Conference, pp. 75-81.
Elms Richard
Luu Pho
Motorola Inc.
LandOfFree
Dual in-laid integrated circuit structure with selectively posit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual in-laid integrated circuit structure with selectively posit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual in-laid integrated circuit structure with selectively posit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1640485