Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-05-01
2003-10-28
Kielin, Erik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S626000, C438S627000, C438S629000, C438S637000, C438S687000
Reexamination Certificate
active
06638851
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the use of a dual hardmask single damascene integration scheme in an organic low k ILD (interlayer dielectric) to affect patterning of single damascene features without feature to feature short circuits due to hardmask erosion in the patterned etched process. The process also permits photoresist removal in an oxidizing plasma without attack of the organic ILD materials.
2. Description of Prior Art
Dual hardmasks have been used extensively in dual damascene structures with organic ILD materials; however, they are employed principally to allow formation of the dual damascene structure without the requirement for an etch stop layer between the line and the via ILD's.
Further, single hardmask for single damascene structures in organic ILD material is known; however, it has been demonstrated that this known approach is insufficient with sub 0.18 &mgr;m features and does not allow removal of the photoresist without attacking the organic ILD.
In general, a damascene process is one kind of interconnect process. The damascene process forms the trench in a dielectric layer. Thereafter, a metal layer is formed in the trench to form a conductive line as an interconnect.
A dual damascene process is one kind of multilevel interconnect process, in which a contact or a via is additionally formed as an interconnect.
FIGS. 1-5
show schematics of cross-sectional views of a prior art damascene process.
From
FIG. 1
, it can be seen that a semiconductor substrate
10
has a dielectric layer
11
formed thereon. By use of a chemical-mechanical polishing (CMP) process, the dielectric layer
11
is planarized. On top of the planarized dielectric layer is a patterned photoresist layer
12
.
By using the photoresist layer
12
as a mask, as shown in
FIG. 2
, the dielectric layer
11
is etched by dry etching to form a trench
13
.
The photoresist layer
12
, as shown in
FIG. 3
is removed by an oxygen plasma, and a metal plug
14
is formed in the trench
13
to complete the damascene process. When a dual damascene process is performed, the process becomes more complicated.
For example, in the conventional process, an oxide with a low dielectric coefficient is used as the dielectric layer
11
. Further, the oxide layer usually includes the spin-on polymer (SOP) characterized by a polymer-like structure. When removing the photoresist layer with oxygen plasma, the SOP layer characterized by the polymer-like structure is readily damaged by the oxygen plasma. Accordingly, the process is not workable for removing the photoresist layer by oxygen plasma.
This being the case, an improved process is to form a cap oxide layer between the dielectric layer and the photoresist layer as shown in another conventional damascene process in the schematics of
FIGS. 4 and 5
.
As may be seen from
FIG. 4
, a dielectric layer
11
is formed over a substrate
10
, whereupon a cap oxide layer
15
is formed on the dielectric layer
11
. A patterned photoresist layer
12
is formed on the cap oxide layer
15
.
From
FIG. 5
, it can be seen that the photoresist layer
12
has been removed by an oxygen plasma. Thereafter, using the cap oxide layer
15
as a hard mask, the dielectric layer
11
is etched to form a trench
13
.
In the traditional or conventional method, use of the cap oxide layer
15
, makes the process more complicated. Further, when etching the dielectric oxide layer with a low dielectric coefficient to form the trench, a gas with oxygen is typically used as the etching gas source. However, when using a gas with oxygen, the dielectric layer is readily damaged during the etching process.
U.S. Pat. No. 6,197,678 B1 disclose a damascene process comprising:
providing a semiconductor substrate;
forming a patterned mask layer over the substrate;
forming a spin-on polymer layer on a portion of the substrate exposed by the mask layer, wherein an upper surface of the spin-on polymer layer is lower than an upper surface of the mask layer upon formation and the spin-on polymer layer does not cover the upper surface of the mask layer;
removing the mask layer to form an opening in the spin-on polymer layer;
forming a conformal barrier layer on the substrate and the spin-on polymer layer; and
forming a metal plug in the opening.
A method is provided for forming an improved interconnect structure on a semiconductor body in U.S. Pat. No. 6,187,672 B1. The method comprises:
(a) depositing a first metal layer on a semiconductor body;
(b) depositing a sacrificial layer on the first metal layer, the sacrificial layer having a height;
(c) patterning the sacrificial layer and the first metal layer to form separate metal lines with a sacrificial layer cap on the metal lines;
(d) depositing a low-k material to fill gaps between the metal lines and to cover the sacrificial layer;
(e) removing the low-k material to a level within the height of the sacrificial layer;
(f) removing the sacrificial layer;
(g) depositing a protective layer to cover the metal lines and the low-k material
(h) depositing an insulator on the protective layer; depositing and patterning a photoresist layer on the insulator;
(i) creating vias in the insulator;
(j) performing a photoresist strip
(k) performing a set clean; and
(l) selectively etching the protective layer using an anisotropic etch configured to leave a spacer on a vertical portion of the low-k material in the vias.
U.S. Pat. No. 6,027,995 disclose a method for fabricating an interconnect system, comprising:
a. providing a silicon substrate;
b. forming a first dielectric layer upon the silicon substrate;
c. forming a first level of at least two electrically conductive lines upon the first dielectric layer;
d. forming a first region of low dielectric constant material upon and between the at least two first level electrically conductive lines, the dielectric constant of the material forming the first region of low dielectric constant material having a range of 1.5 to 3.5; and
e. forming a hard mask upon the first region, wherein a thickness of the first region material measured between the first dielectric layer and the hard mask is in the range of 8,000 to 14,000 Angstroms.
There is a need in the art of preparing microelectronic devices, especially in the BEOL (back-end-of-the-line) semiconductor structures to provide an inorganic (silicon oxide and silicon nitride) dual hard mask in a single damascene integration scheme to allow: removal of the photoresist masking material in an oxidizing plasma without attack of the organic ILD material.
There is a further need in the art of fabricating semiconductor devices of the BEOL (back-end-of-the-line) structures to employ an inorganic (silicon oxide and silicon nitride) dual hard mask in a single damascene integration scheme to allow: prevention of feature to feature short circuits by using a sacrificial hard mask which is eroded during the organic ILD etch process that is subsequently removed by CMP (chemical mechanical polishing).
SUMMARY OF THE INVENTION
One object of the present invention is to provide a dual hard mask single damascene integration scheme in an organic low k ILD to allow removal of the photoresist masking material in an oxidizing plasma without attack of the organic ILD material.
A further object of the present invention is to provide a dual hard mask single damascene integration scheme in an organic low k ILD to allow prevention of feature-to-feature short circuits by using a sacrificial hard mask which is eroded during the organic ILD etch process and is subsequently removed by CMP (chemical mechanical polishing).
These and other objects of the invention will be more fully appreciated by resorting to the drawing figures and the detailed description of the preferred embodiment of the invention.
REFERENCES:
patent: 5858869 (1999-01-01), Chen et al.
patent: 6027995 (2000-02-01), Chiang et al.
patent: 6114253 (2000-09-01), Jang et al.
patent: 6117782 (2000-09-01), Lukanc et al.
patent: 6140225 (2000-10-01), Usami et al.
patent: 6140706 (2000-10
Cowley Andy
Kaltalioglu Erdem
Stetter Michael
Infineon Technologies North America Corp.
Kielin Erik
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