Dual-gate, sonos, non-volatile memory cells and arrays thereof

Details Dual-gate, sonos, non-volatile memory cells and arrays thereof Dual-gate, sonos, non-volatile memory cells and arrays thereof

2011-07-05

2011-07-05

Andújar, Leonardo (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29309, C438S157000

Reexamination Certificate

active

07973366

ABSTRACT:
Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

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