Dual-gate SOI transistor

Details Dual-gate SOI transistor Dual-gate SOI transistor

1998-02-18

1999-12-21

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438159, H01L 2100

Patent

active

060048379

ABSTRACT:
A dual-gate SOI transistor has self-aligned upper and lower gates, in which a gate trench that will hold the dual-gate structure is formed by damaging the oxide under the transistor active area and preferentially etching that damaged region with HF, thus producing a self-aligned opening that has less overlap of the lower gate and the source/drain junctions and is filled with LPCVD polysilicon to form a dual-gate structure having reduced capacitance compared with prior art devices.

REFERENCES:
patent: 5120666 (1992-06-01), Gotou
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5578513 (1996-11-01), Maegawa
patent: 5646058 (1997-07-01), Taur et al.
patent: 5926699 (1999-07-01), Hayahsi et al.
patent: 5933736 (1999-08-01), Nakaumura

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