Dual gate semiconductor device for shortening channel length

Details Dual gate semiconductor device for shortening channel length Dual gate semiconductor device for shortening channel length

1998-03-31

2001-02-13

Abraham, Fetsum (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S260000, C257S270000, C257S318000, C257S331000, C257S369000

Reexamination Certificate

active

06188111

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device, and in particular, to a MOSFET which is formed over a SOI (Silicon On Insulator) substrate.
Conventionally, a MOS transistor is often formed on an insulator as a thin-film semiconductor device by the use of the known SOI substrate.
Specifically, an oxide film (namely, an insulator) is embedded in a silicon substrate. Further, an active region (a silicon layer) is formed on the oxide film. In this event, a source diffusion layer, a drain diffusion layer and a channel region are formed in the active region, respectively. Moreover, a gate region is formed over the channel region via a gate oxide film. Herein, the gate region is formed by a polysilicon. In addition, side walls are formed at both side surfaces of the gate region.
In this case, the source and drain diffusion layers are formed by implanting or doping impurity ions after patterning the gate region and forming the side walls. Herein, the ion implantation is carried out by using the gate region and the side walls as a mask in the known self-alignment manner. Consequently, the channel length which determines the performance of the MOS transistor is determined by fine process accuracy of the gate region and the side walls.
In this event, the gate region is generally formed by the following processes.
(1) Growth of a gate electrode (polysilicon)
(2) Application of a photoresist
(3) Patterning of the photoresist
(4) Etching of the gate electrode
The gate length is mainly determined by (3) the patterning of the photoresist and (4) the etching of the gate electrode.
Recently, the semiconductor device having the gate length of 0.35 &mgr;m level is practically used. However, as the gate length is further shortened, it becomes difficult to keep the process accuracy in the conventional MOS transistor.
On the other hand, a CMOS circuit is often structured as an inverter by the MOS transistors (an N-channel MOS transistor and a P-channel MOS transistor). Further, a latch circuit is constituted by connecting a plurality of CMOS circuits. In this case, the diffusion layer in the active region is connected to the gate region by the use of a wiring layer. Consequently, the layout area of the circuit is increased to reduce integration degree of the device because the wiring layer is additionally required to connect between the diffusion layer and the gate region.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a semiconductor device which is capable of shortening a channel length of a MOS transistor.
It is another object of this invention to provide a semiconductor device which is capable of reducing a layout area to increase integration degree in a logic circuit.
According to a semiconductor device including a MOS transistor, a first semiconductor layer is formed over a silicon substrate and has a gate region. Further, a second semiconductor layer is formed over the first semiconductor layer via a gate oxide film and has an active region. Herein, the active region has a source region, a drain region and a channel region. The channel region is placed between the source region and the drain region and over the gate region.
By adopting the above structure, the number of the manufacturing steps which give a large influence to determine the channel length is reduced as compared to the conventional semiconductor device. Consequently, the channel length can be further reduced.
Further, a wiring layer (namely, a back gate) is formed over the channel region so as to control potential of the channel region. The back gate can be easily formed by the use of the metal wiring layer which is formed by the normal process. The circuit characteristic can be controlled by controlling the potential of the back gate.
Moreover, according to a semiconductor device constituting a latch circuit, the latch circuit has a first CMOS circuit and a second CMOS circuit. The first CMOS circuit includes a first semiconductor layer which is formed over a silicon substrate and a second semiconductor layer which is formed over said first semiconductor layer. In this event, the first semiconductor layer has a first active region while the second semiconductor layer has a first gate region.
On the other hand, the second CMOS circuit includes a third semiconductor layer which is formed over the silicon substrate and a fourth semiconductor layer which is formed over the third semiconductor layer. In this event, the third semiconductor layer has a second gate region while the fourth semiconductor layer has a second active region.
In this event, the first semiconductor layer is directly coupled to or integrated with the third semiconductor layer. Specifically, each of the first and third semiconductor layers is formed by the silicon layer while each of the second and fourth semiconductor layers is formed by the polysilicon layer. With such a structure, the metal wiring area in the circuit block can be reduced to increase the integration degree of the device.


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