Dual-gate resurf superjunction lateral DMOSFET

Details Dual-gate resurf superjunction lateral DMOSFET Dual-gate resurf superjunction lateral DMOSFET

2000-08-31

2003-03-04

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000, C257S335000, C257S401000

Reexamination Certificate

active

06528849

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to power semiconductor devices, and in particular relates to power MOSFETs.
BACKGROUND OF THE INVENTION
A fundamental consideration in the design of integrated circuits is the physical size of the electrical components to be included on the integrated circuits. The value of an integrated circuit increases as the size of the electrical components on the integrated circuit decreases, since the number of electrical components that can be included on a given integrated circuit increases as the physical size of the electrical components is reduced.
Integrated circuits often include different types of electrical components, ranging from logic components (e.g., flip-flops) and analog components (e.g., NPN bipolar junction transistors) to power electronics components such as power MOSFETs (metal-oxide-semiconductor field-effect transistors). Although recent improvements in the design of integrated circuits have led to reductions in size for each of these types of electrical components, there has grown a disparity in the rates of size reduction between different types of electrical components. In particular, where in certain instances the sizes of logic components have been reduced by two orders of magnitude, the sizes of power components have only been reduced one or less order of magnitude.
That the rates of size reduction of power components on integrated circuits have been lower than the rates of size reduction for some other integrated circuit components is significant. On many integrated circuits, power components already take up one-third to one-half of the total area of the integrated circuits. As the sizes of other types of electrical components continue to shrink at a faster rate than the sizes of power components, the proportion of the total area of integrated circuits that is taken up by power components continues to increase. Thus, the rates of reduction in the overall sizes of integrated circuits are being increasingly limited by the slow rates of size reduction concerning power components.
A figure of merit that is commonly employed as an indication of the relative sizes of power components on integrated circuits is the specific on-resistance, which is defined as the resistance of the power component when it is conducting current in its on state, multiplied by the area of the power component. Minimization of the specific on-resistance of a power component corresponds to minimization of the area, and consequently the size, of the power component. One type of power component for which reductions in specific on-resistance (and consequently reductions in size) have become increasingly difficult is the lateral DMOSFET, which is a double-diffused metal-oxide-semiconductor field-effect transistor, and which is “lateral” insofar as the active, conducting portions of the DMOSFET are all located along a top surface of the device.
Reductions in the specific on-resistance of the lateral DMOSFET are difficult largely because it is typically desirable for the DMOSFET to have a high breakdown voltage (BV
dss
) so that the DMOSFET can sustain high voltages applied between its drain and source terminals in its off state without conducting current. In order to have a high breakdown voltage, a conventional lateral DMOSFET typically requires a long drift region between the source and drain regions of the lateral DMOSFET, which increases the specific on-resistance (and size) of the lateral DMOSFET. Although reduced doping of the drift region also tends to increase the breakdown voltage, such reduced doping of the drift region is counterproductive insofar as it tends to further increase the specific on-resistance. Further, size reductions in the cross sectional width of the drift region (perpendicular to the axis connecting the drain and source terminals) are not effective for reducing the specific on-resistance because, in addition to reducing the area of the drift region, such size reductions also tend to reduce the conductivity and increase the resistance of the drift region when the lateral DMOSFET is in its on state. Increased resistance within the drift region is particularly undesirable because it increases the power consumption and heat dissipation of the lateral DMOSFET when it is operating in its on state.
Referring to
FIG. 1
(Prior Art), schematically one embodiment of a conventional NMOS lateral DMOSFET
10
includes a source region
12
that is doped with P+ type impurities, a drift region
14
that is doped with N− type impurities, and a drain region
16
that is doped with N+ type impurities. As shown by a first curve
22
in
FIG. 2
(Prior Art), when the lateral DMOSFET
10
is in its off state (because the voltage applied between the gate and source of the DMOSFET is zero) and a positive voltage is applied between the drain region
16
and the source region
12
, a nonzero electric field is created within the drift region
14
. The electric field varies approximately linearly from a maximum occurring at or near a junction
18
between the source region
12
and the drift region
14
and a minimum (e.g., zero electric field) occurring at a point
24
somewhere along the drift region.
The voltage applied to the lateral DMOSFET
10
between the drain region
16
and the source region
12
exceeds the breakdown voltage when the voltage becomes sufficiently large such that the maximum electric field exceeds a critical level, for example, 40 Volts per micron. Consequently, the lateral DMOSFET must be designed so that, given off state voltages between the drain region
16
and the source region
12
that are below the desired breakdown voltage, the maximum electric field does not exceed the critical level. As the length of the drift region
14
decreases, the critical level of the electric field is attained at a lower voltage. As a result, for the lateral DMOSFET to be able to sustain a desired breakdown voltage, the length of the drift region must be maintained above a minimum length. Further, as a result of the need for the drift region length to be maintained above a certain minimum length, the specific on-resistance is compromised, and hence there is a fundamental tradeoff between the specific on-resistance and the breakdown voltage.
It is known in the art to modify the simple NMOS lateral DMOSFET discussed above in several ways so that the specific on-resistance of the DMOSFET can be reduced without compromising the desired high breakdown voltage. One known modification is to provide an additional layer of silicon doped with P− type impurities underneath the drift region
14
, which is shown in
FIG. 1
as a RESURF region
32
. Such a modified lateral DMOSFET is termed a NMOS Reduced Surface Field (RESURF) lateral DMOSFET
20
. The RESURF lateral DMOSFET
20
can have the same breakdown voltage as, and a lower specific on-resistance than, a simple lateral DMOSFET because extra depletion of electrons occurs from the drift region of the RESURF lateral DMOSFET when the DMOSFET is in its off state. Specifically, extra depletion occurs due to the interaction of the drift region
14
with the RESURF region
32
, in addition to the normal depletion that occurs between the drift region and the source region
12
.
As shown by curve
28
of
FIG. 2
, the extra depletion within the RESURF lateral DMOSFET
20
causes the nonzero electric field to be distributed throughout the drift region
14
such that the electric field distribution is flattened and, in particular, reduces the maximum electric field that occurs at any point within the drift region. Specifically, given the application of the same voltage between the drain region
16
and source region
12
of the RESURF lateral DMOSFET
20
as assumed with respect to the simple lateral DMOSFET
10
discussed above (where both DMOSFETs have drift regions of equal dimensions), the resulting electric field within the drift region
14
is lower at the junction
18
for the RESURF lateral DMOSFET than for the simple lateral DMOSFET. With the adding of the

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