Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-12-15
2002-03-19
Pham, Long (Department: 2323)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S440000, C438S449000, C438S283000, C438S287000, C148SDIG001
Reexamination Certificate
active
06358819
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method for fabricating a dual gate oxide for deep submicron integrated circuit systems (ICS) using non-critical photolithographic masking to select implantation areas followed by oxygen ion implantation into the selected areas.
2. Description of Related Art
The increasing diversity of design requirements for metal oxide semiconductor (MOS) devices, such as dual voltage requirements on chip input/output, the need to tolerate higher voltages, and the need to handle higher power supply inputs, has driven the semiconductor industry towards the increased use of gate oxide layers of different thicknesses. A number of methods have been proposed to meet this demand. For example, U.S. Pat. No. 5,273,921 (Neudeck, et al.) proposes several methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor. By in large, however, present techniques for dual-gated oxide processes have several complex processing steps, some of which entail high processing temperatures. The heat treatment steps typically expose the device to temperatures in the range of 600 to 1000° C. for as long as 4 hours. The present methods for producing dual-gate oxides are, therefore, undesirable not only for the additional time and expense added to the processing due to the complexity of the procedures, but also because of the undesirability of the high processing temperatures, which are difficult to accommodate in device designs in light of the undesired diffusion of impurities caused by heat exposure. The criticality of wet etch processing and other complexities in the various present art dual-gate oxide processes further makes the uniformity of the oxide layers difficult to precisely control, thus leading to quality control problems.
Accordingly, a need exists for a relatively simple method of accomplishing a dual-gate oxide device architecture. Preferably, this method should reduce the criticality of wet clean/oxide etch back steps as well as reduce the need for high processing temperatures. A desirable dual-gate oxide process would reduce the complexity of creating MOS integrated circuits with two or more different gate oxide thicknesses to a few simple steps and allow for control of the final thickness and uniformity independent of ambient flow pattern characteristics and the variable delivery of oxidizing species to the surface of the wafer.
SUMMARY OF THE INVENTION
A method for fabricating a dual-gate oxide for MOS devices is disclosed using a photoresist masking layer applied after the first layer of gate oxide is grown on the wafer. The photoresist layer is removed from areas where thicker gate oxide material is desired. A low energy implantation of oxygen ions is then performed. The remaining photoresist is removed and the surface is cleaned followed by a heat treatment, thus resulting in the oxidation of the silicon of the surface underneath the gate oxide material.
This invention reduces the complexity of creating MOS integrated circuits with two different gate oxide thicknesses to a simple photolithography step combined with an ion implantation technique. The criticality of wet etch processing of present state of the art processes is eliminated or substantially reduced. The final thickness uniformity is independent of ambient flow pattern characteristics and variable delivery of oxidizing species to the surface of the wafer. Since the invention does not involve several high processing temperature steps, the undesired diffusion of impurity is avoided.
The above as well as additional features and advantages of the present invention will become apparent in the following written detailed description.
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Miller Gayle W.
Shelton Gail D.
Hawranek Scott J.
LSI Logic Corporation
Pham Long
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